riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

better handling of lut and begin/end add

This commit is contained in:
Miodrag Milanovic 2019-09-18 17:45:07 +02:00
parent 3487b95224
commit 8badd4d812
1 changed files with 10 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
techlibs/efinix/cells_sim.v
View File

@ -5,8 +5,12 @@ module EFX_LUT4(
input I2,
input I3
);
parameter LUTMASK = 16'h0000;
assign O = LUTMASK >> {I3, I2, I1, I0};
parameter LUTMASK = 16'h0000;
wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module EFX_ADD(
@ -71,10 +75,12 @@ module EFX_FF(
begin
always @(posedge clk)
if (ce)
begin
if (sr)
Q <= SR_VALUE;
else
Q <= d;
Q <= d;
end
end
end
else
@ -164,4 +170,4 @@ module EFX_RAM_5K(
(WRITE_WIDTH == 10) ? 9 : // 512x10
(WRITE_WIDTH == 5) ? 10 : -1; // 1024x5
endmodule
endmodule