Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0

2020-01-22 14:22:03 -08:00 · 2020-01-22 14:22:03 -08:00 · 7858cf20a9
parent da6abc0149
commit 7858cf20a9
1 changed files with 1 additions and 1 deletions
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@ -42,7 +42,7 @@ endmodule
 // Box to emulate async behaviour of FDP*
 (* abc9_box_id = 1001, lib_whitebox *)
 module \$__ABC9_ASYNC1 (input A, S, output Y);
-  assign Y = S ? 1'b0 : A;
+  assign Y = S ? 1'b1 : A;
 endmodule

 // Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}