mirror of https://github.com/YosysHQ/yosys.git
Wrap LUTRAMs in order to capture comb/seq behaviour
This commit is contained in:
Eddie Hung
parent
c00d72cdb3
commit
808f07630f
|
|
@ -118,3 +118,72 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
|
|||
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
|
||||
\$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
|
||||
endmodule
|
||||
|
||||
module RAM32X1D (
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
|
||||
);
|
||||
parameter INIT = 32'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
wire \$DPO , \$SPO ;
|
||||
\$__ABC_RAM32X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(\$DPO ), .SPO(\$SPO ),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
||||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
|
||||
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
|
||||
);
|
||||
\$__ABC_LUTMUX dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
|
||||
\$__ABC_LUTMUX spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
|
||||
endmodule
|
||||
|
||||
module RAM64X1D (
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
parameter INIT = 64'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
wire \$DPO , \$SPO ;
|
||||
\$__ABC_RAM64X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(\$DPO ), .SPO(\$SPO ),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
||||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
|
||||
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
|
||||
);
|
||||
\$__ABC_LUTMUX6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
|
||||
\$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
|
||||
endmodule
|
||||
|
||||
module \$__ABC_RAM128X1D (
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input [6:0] A, DPRA
|
||||
);
|
||||
parameter INIT = 128'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
wire \$DPO , \$SPO ;
|
||||
\$__ABC_RAM128X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(\$DPO ), .SPO(\$SPO ),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
||||
.A(A),
|
||||
.DPRA(DPRA)
|
||||
);
|
||||
\$__ABC_LUTMUX7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
|
||||
\$__ABC_LUTMUX7 spo (.A(\$SPO ), .S(A), .Y(SPO));
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -113,3 +113,47 @@ module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
|
|||
parameter EN_POLARITY = 1'b1;
|
||||
assign Q = (CE && !PRE) ? D : \$pastQ ;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id=2000 *)
|
||||
module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
|
||||
endmodule
|
||||
(* abc_box_id=2001 *)
|
||||
module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
|
||||
endmodule
|
||||
|
||||
|
||||
module \$__ABC_RAM32X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
||||
(* abc_arrival=1472 *) output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_RAM64X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
||||
(* abc_arrival=1472 *) output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
parameter INIT = 64'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
endmodule
|
||||
|
||||
module \$__ABC_RAM128X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
||||
(* abc_arrival=1472 *) output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input [6:0] A, DPRA
|
||||
);
|
||||
parameter INIT = 128'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -138,3 +138,67 @@ module \$__ABC_FDPE_1 (output Q,
|
|||
.D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_LUTMUX (input A, input [5:0] S, output Y);
|
||||
assign Y = A;
|
||||
endmodule
|
||||
|
||||
module \$__ABC_RAM32X1D (
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
|
||||
);
|
||||
parameter INIT = 32'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
RAM32X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(DPO), .SPO(SPO),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
||||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
|
||||
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_RAM64X1D (
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
parameter INIT = 64'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
RAM64X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(DPO), .SPO(SPO),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
||||
.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
|
||||
.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module \$__ABC_RAM128X1D (
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
input WE,
|
||||
input A,
|
||||
input DPRA,
|
||||
);
|
||||
parameter INIT = 128'h0;
|
||||
parameter IS_WCLK_INVERTED = 1'b0;
|
||||
RAM128X1D #(
|
||||
.INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.DPO(DPO), .SPO(SPO),
|
||||
.D(D), .WCLK(WCLK), .WE(WE),
|
||||
.A(A),
|
||||
.DPRA(DPRA)
|
||||
);
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -38,27 +38,6 @@ CARRY4 4 1 10 8
|
|||
592 540 520 356 - 512 548 292 - 228
|
||||
580 526 507 398 385 508 528 378 380 114
|
||||
|
||||
# SLICEM/A6LUT
|
||||
# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
|
||||
# Outputs: DPO SPO
|
||||
RAM32X1D 5 0 13 2
|
||||
- - - - - - 631 472 407 238 127 - -
|
||||
631 472 407 238 127 - - - - - - - -
|
||||
|
||||
# SLICEM/A6LUT
|
||||
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
|
||||
# Outputs: DPO SPO
|
||||
RAM64X1D 6 0 15 2
|
||||
- - - - - - - 642 631 472 407 238 127 - -
|
||||
642 631 472 407 238 127 - - - - - - - - -
|
||||
|
||||
# SLICEM/A6LUT + F7[AB]MUX
|
||||
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
|
||||
# Outputs: DPO SPO
|
||||
RAM128X1D 7 0 17 2
|
||||
- - - - - - - - 1009 998 839 774 605 494 450 - -
|
||||
1047 1036 877 812 643 532 478 - - - - - - - - - -
|
||||
|
||||
# Box to emulate async behaviour of FD[CP]*
|
||||
# Inputs: A S
|
||||
# Outputs: Y
|
||||
|
|
@ -99,3 +78,17 @@ FDPE 1005 1 5 1
|
|||
# Outputs: Q
|
||||
FDPE_1 1006 1 5 1
|
||||
0 151 0 806 0
|
||||
|
||||
# SLICEM/A6LUT
|
||||
# Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
|
||||
# Inputs: A S0 S1 S2 S3 S4 S5
|
||||
# Outputs: Y
|
||||
$__ABC_LUTRAM6 2000 0 7 1
|
||||
0 642 631 472 407 238 127
|
||||
|
||||
# SLICEM/A6LUT + F7BMUX
|
||||
# Box to emulate comb/seq behaviour of RAMD128
|
||||
# Inputs: A S0 S1 S2 S3 S4 S5 S6
|
||||
# Outputs: DPO SPO
|
||||
$__ABC_LUTRAM7 2001 0 8 1
|
||||
0 1047 1036 877 812 643 532 478
|
||||
|
|
|
|||
|
|
@ -287,13 +287,11 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
|
|||
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 5 *)
|
||||
module RAM32X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
||||
(* abc_arrival=1472 *) output DPO, SPO,
|
||||
(* abc_scc_break *) input D,
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
(* abc_scc_break *) input WE,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
|
||||
);
|
||||
|
|
@ -308,13 +306,11 @@ module RAM32X1D (
|
|||
always @(posedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 6 *)
|
||||
module RAM64X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
||||
(* abc_arrival=1472 *) output DPO, SPO,
|
||||
(* abc_scc_break *) input D,
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
(* abc_scc_break *) input WE,
|
||||
input WE,
|
||||
input A0, A1, A2, A3, A4, A5,
|
||||
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
|
||||
);
|
||||
|
|
@ -329,13 +325,11 @@ module RAM64X1D (
|
|||
always @(posedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 7 *)
|
||||
module RAM128X1D (
|
||||
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
|
||||
(* abc_arrival=1472 *) output DPO, SPO,
|
||||
(* abc_scc_break *) input D,
|
||||
output DPO, SPO,
|
||||
input D,
|
||||
input WCLK,
|
||||
(* abc_scc_break *) input WE,
|
||||
input WE,
|
||||
input [6:0] A, DPRA
|
||||
);
|
||||
parameter INIT = 128'h0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue