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FDCE ports to be alphabetical

This commit is contained in:
Eddie Hung 2019-12-31 15:24:02 -08:00
parent b4663a987b
commit 4cdba00e25
1 changed files with 3 additions and 3 deletions
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6
techlibs/xilinx/cells_sim.v
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@ -405,10 +405,10 @@ module FDCE (
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input CE,
(* invertible_pin = "IS_D_INVERTED" *)
input D,
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR
input CLR,
(* invertible_pin = "IS_D_INVERTED" *)
input D
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;