mirror of https://github.com/YosysHQ/yosys.git
Add LP timings
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@ -174,11 +174,13 @@ module \$__ICE40_CARRY_WRAPPER (
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endmodule
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// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
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// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
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// Positive Edge SiliconBlue FF Cells
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module SB_DFF (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, D
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);
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@ -188,6 +190,7 @@ endmodule
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module SB_DFFE (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, E, D
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);
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@ -198,6 +201,7 @@ endmodule
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module SB_DFFSR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, R, D
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);
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@ -210,6 +214,7 @@ endmodule
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module SB_DFFR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, R, D
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);
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@ -222,6 +227,7 @@ endmodule
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module SB_DFFSS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, S, D
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);
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@ -234,6 +240,7 @@ endmodule
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module SB_DFFS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, S, D
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);
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@ -246,6 +253,7 @@ endmodule
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module SB_DFFESR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, E, R, D
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);
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@ -260,6 +268,7 @@ endmodule
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module SB_DFFER (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, E, R, D
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);
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@ -272,6 +281,7 @@ endmodule
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module SB_DFFESS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, E, S, D
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);
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@ -286,6 +296,7 @@ endmodule
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module SB_DFFES (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, E, S, D
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);
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@ -300,6 +311,7 @@ endmodule
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module SB_DFFN (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, D
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);
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@ -309,6 +321,7 @@ endmodule
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module SB_DFFNE (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, E, D
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);
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@ -319,6 +332,7 @@ endmodule
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module SB_DFFNSR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, R, D
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);
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@ -331,6 +345,7 @@ endmodule
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module SB_DFFNR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, R, D
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);
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@ -343,6 +358,7 @@ endmodule
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module SB_DFFNSS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, S, D
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);
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@ -355,6 +371,7 @@ endmodule
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module SB_DFFNS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, S, D
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);
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@ -367,6 +384,7 @@ endmodule
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module SB_DFFNESR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, E, R, D
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);
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@ -381,6 +399,7 @@ endmodule
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module SB_DFFNER (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, E, R, D
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);
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@ -393,6 +412,7 @@ endmodule
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module SB_DFFNESS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, E, S, D
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);
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@ -407,6 +427,7 @@ endmodule
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module SB_DFFNES (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output `SB_DFF_REG,
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input C, E, S, D
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);
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@ -421,6 +442,7 @@ endmodule
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module SB_RAM40_4K (
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`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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@ -590,6 +612,7 @@ endmodule
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module SB_RAM40_4KNR (
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`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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output [15:0] RDATA,
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input RCLKN, RCLKE, RE,
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input [10:0] RADDR,
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@ -656,6 +679,7 @@ endmodule
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module SB_RAM40_4KNW (
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`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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@ -722,6 +746,7 @@ endmodule
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module SB_RAM40_4KNRNW (
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`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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output [15:0] RDATA,
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input RCLKN, RCLKE, RE,
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input [10:0] RADDR,
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@ -792,6 +817,7 @@ module ICESTORM_LC (
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input I0, I1, I2, I3, CIN, CLK, CEN, SR,
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output LO,
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(795)
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output O,
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output COUT
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);
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