Re-enable &mfs for synth_{ecp5,xilinx}

This commit is contained in:
Eddie Hung 2020-01-06 16:21:04 -08:00
parent 3753760971
commit 53aa51dc92
2 changed files with 2 additions and 3 deletions

View File

@ -323,9 +323,9 @@ struct SynthEcp5Pass : public ScriptPass
if (abc9) {
run("read_verilog -icells -lib +/ecp5/abc9_model.v");
if (nowidelut)
run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
else
run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
run("techmap -map +/ecp5/abc9_unmap.v");
} else {
if (nowidelut)

View File

@ -541,7 +541,6 @@ struct SynthXilinxPass : public ScriptPass
run("read_verilog -icells -lib +/xilinx/abc9_model.v");
std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
abc9_opts += " -nomfs";
if (nowidelut)
abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
else