mirror of https://github.com/YosysHQ/yosys.git
Re-enable &mfs for synth_{ecp5,xilinx}
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3753760971
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@ -323,9 +323,9 @@ struct SynthEcp5Pass : public ScriptPass
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if (abc9) {
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run("read_verilog -icells -lib +/ecp5/abc9_model.v");
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if (nowidelut)
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run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
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run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
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else
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run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
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run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
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run("techmap -map +/ecp5/abc9_unmap.v");
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} else {
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if (nowidelut)
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@ -541,7 +541,6 @@ struct SynthXilinxPass : public ScriptPass
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run("read_verilog -icells -lib +/xilinx/abc9_model.v");
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std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
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abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
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abc9_opts += " -nomfs";
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if (nowidelut)
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abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
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else
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