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remove duplicate DFFR
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@ -38,16 +38,6 @@ module DFFN (output reg Q, input CLK, D);
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Q <= D;
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endmodule
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module DFFR (output reg Q, input D, CLK, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFR (positive clock edge; synchronous reset)
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module DFFE (output reg Q, input D, CLK, CE);
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parameter [0:0] INIT = 1'b0;
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