diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index b70d1299c..de0cfa9f3 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -38,16 +38,6 @@ module DFFN (output reg Q, input CLK, D);
 		Q <= D;
 endmodule
 
-module DFFR (output reg Q, input D, CLK, RESET);
-	parameter [0:0] INIT = 1'b0;
-	initial Q = INIT;
-	always @(posedge CLK) begin
-        if (RESET)
-                Q <= 1'b0;
-        else
-                Q <= D;
-	end
-endmodule // DFFR (positive clock edge; synchronous reset)
 
 module DFFE (output reg Q, input D, CLK, CE);
   parameter [0:0] INIT = 1'b0;