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Add arrival times for SRL outputs

This commit is contained in:
Eddie Hung 2019-08-19 15:15:43 -07:00
parent 45d4b33f0c
commit 526e081342
1 changed files with 5 additions and 3 deletions
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8
techlibs/xilinx/cells_sim.v
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@ -353,7 +353,8 @@ module RAM128X1D (
endmodule
module SRL16E (
output Q,
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc_arrival=1472 *) output Q,
input A0, A1, A2, A3, CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
@ -371,8 +372,9 @@ module SRL16E (
endmodule
module SRLC32E (
output Q,
output Q31,
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc_arrival=1472 *) output Q,
(* abc_arrival=1114 *) output Q31,
input [4:0] A,
input CE, CLK, D
);