mirror of https://github.com/YosysHQ/yosys.git
mul2dsp.v slice names
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@ -129,14 +129,14 @@ module _80_mul (A, B, Y);
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wire [Y_WIDTH-1:0] partial_sum [n:0];
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end
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for (i = 0; i < n; i=i+1) begin:slice
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for (i = 0; i < n; i=i+1) begin:sliceA
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\$__mul #(
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.A_SIGNED(sign_headroom),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(`DSP_A_MAXWIDTH_PARTIAL),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(partial_Y_WIDTH)
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) mul_slice (
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) mul (
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.A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH_PARTIAL-sign_headroom) +: `DSP_A_MAXWIDTH_PARTIAL-sign_headroom]}),
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.B(B),
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.Y(partial[i])
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@ -165,7 +165,7 @@ module _80_mul (A, B, Y);
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.A_WIDTH(last_A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(last_Y_WIDTH)
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) mul_slice_last (
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) sliceA.last (
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.A(A[A_WIDTH-1 -: last_A_WIDTH]),
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.B(B),
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.Y(last_partial)
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@ -194,7 +194,7 @@ module _80_mul (A, B, Y);
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wire [Y_WIDTH-1:0] partial_sum [n:0];
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end
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for (i = 0; i < n; i=i+1) begin:slice
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for (i = 0; i < n; i=i+1) begin:sliceB
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\$__mul #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(sign_headroom),
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@ -230,7 +230,7 @@ module _80_mul (A, B, Y);
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(last_B_WIDTH),
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.Y_WIDTH(last_Y_WIDTH)
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) mul_last (
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) mul_sliceB_last (
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.A(A),
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.B(B[B_WIDTH-1 -: last_B_WIDTH]),
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.Y(last_partial)
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