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@ -597,10 +597,10 @@ module DSP48E1 (
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else assign B_muxed = B;
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endgenerate
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reg signed [29:0] Ar1 = 30'b0, Ar2 = 30'b0;
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reg signed [24:0] Dr = 25'b0;
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reg signed [17:0] Br1 = 18'b0, Br2 = 18'b0;
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reg signed [47:0] Cr = 48'b0;
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reg signed [29:0] Ar1, Ar2;
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reg signed [24:0] Dr;
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reg signed [17:0] Br1, Br2;
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reg signed [47:0] Cr;
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reg [4:0] INMODEr = 5'b0;
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reg [6:0] OPMODEr = 7'b0;
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reg [3:0] ALUMODEr = 4'b0;
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@ -609,6 +609,8 @@ module DSP48E1 (
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generate
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// Configurable A register
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if (AREG == 2) begin
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initial Ar1 = 30'b0;
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initial Ar2 = 30'b0;
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always @(posedge CLK)
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if (RSTA) begin
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Ar1 <= 30'b0;
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@ -618,6 +620,8 @@ module DSP48E1 (
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if (CEA2) Ar2 <= Ar1;
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end
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end else if (AREG == 1) begin
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//initial Ar1 = 30'b0;
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initial Ar2 = 30'b0;
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always @(posedge CLK)
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if (RSTA) begin
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Ar1 <= 30'b0;
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@ -633,6 +637,8 @@ module DSP48E1 (
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// Configurable B register
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if (BREG == 2) begin
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initial Br1 = 25'b0;
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initial Br2 = 25'b0;
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always @(posedge CLK)
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if (RSTB) begin
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Br1 <= 18'b0;
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@ -642,6 +648,8 @@ module DSP48E1 (
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if (CEB2) Br2 <= Br1;
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end
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end else if (BREG == 1) begin
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//initial Br1 = 25'b0;
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initial Br2 = 25'b0;
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always @(posedge CLK)
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if (RSTB) begin
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Br1 <= 18'b0;
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@ -656,24 +664,30 @@ module DSP48E1 (
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end
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// C and D registers
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if (CREG == 1) initial Cr = 48'b0;
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if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end
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else always @* Cr <= C;
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if (CREG == 1) initial Dr = 25'b0;
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if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end
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else always @* Dr <= D;
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// Control registers
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if (INMODEREG == 1) initial INMODEr = 5'b0;
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if (INMODEREG == 1) begin always @(posedge CLK) if (RSTINMODE) INMODEr <= 5'b0; else if (CEINMODE) INMODEr <= INMODE; end
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else always @* INMODEr <= INMODE;
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if (OPMODEREG == 1) initial OPMODEr = 7'b0;
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if (OPMODEREG == 1) begin always @(posedge CLK) if (RSTCTRL) OPMODEr <= 7'b0; else if (CECTRL) OPMODEr <= OPMODE; end
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else always @* OPMODEr <= OPMODE;
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if (ALUMODEREG == 1) initial ALUMODEr = 4'b0;
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if (ALUMODEREG == 1) begin always @(posedge CLK) if (RSTALUMODE) ALUMODEr <= 4'b0; else if (CEALUMODE) ALUMODEr <= ALUMODE; end
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else always @* ALUMODEr <= ALUMODE;
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if (CARRYINSELREG == 1) initial CARRYINSELr = 3'b0;
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if (CARRYINSELREG == 1) begin always @(posedge CLK) if (RSTCTRL) CARRYINSELr <= 3'b0; else if (CECTRL) CARRYINSELr <= CARRYINSEL; end
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else always @* CARRYINSELr <= CARRYINSEL;
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endgenerate
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// A and B cascsde
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// A and B cascade
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generate
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if (ACASCREG == 1 && AREG == 2) assign ACOUT = Ar1;
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else assign ACOUT = Ar2;
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@ -686,9 +700,10 @@ module DSP48E1 (
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wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed;
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wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0;
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wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated);
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reg signed [24:0] ADr = 25'b0;
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reg signed [24:0] ADr;
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generate
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if (ADREG == 1) initial ADr = 25'b0;
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if (ADREG == 1) begin always @(posedge CLK) if (RSTD) ADr <= 25'b0; else if (CEAD) ADr <= AD_result; end
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else always @* ADr <= AD_result;
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endgenerate
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@ -860,10 +875,6 @@ module DSP48E1 (
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endgenerate
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wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum;
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initial P = 48'b0;
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initial CARRYOUT = carryout_reset;
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initial CARRYCASCOUT = 1'b0;
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initial MULTSIGNOUT = 1'b0;
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wire [3:0] CARRYOUTd = (OPMODEr[3:0] == 4'b0101 || ALUMODEr[3:2] != 2'b00) ? 4'bxxxx :
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((ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out);
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wire CARRYCASCOUTd = ext_carry_out[3];
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@ -871,6 +882,10 @@ module DSP48E1 (
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generate
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if (PREG == 1) begin
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initial P = 48'b0;
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initial CARRYOUT = carryout_reset;
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initial CARRYCASCOUT = 1'b0;
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initial MULTSIGNOUT = 1'b0;
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always @(posedge CLK)
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if (RSTP) begin
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P <= 48'b0;
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