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Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival

This commit is contained in:
Eddie Hung 2019-08-28 17:19:02 -07:00
parent a45c09c8d1 2aedee1f0e
commit 345a572449
5 changed files with 20 additions and 68 deletions
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8
techlibs/ice40/abc_hx.box
View File

@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
# Inputs: A B CI
# Inputs: A B I0 I3 CI
# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
$__ICE40_FULL_ADDER 1 1 3 2
400 379 316
259 231 126
$__ICE40_FULL_ADDER 1 1 5 2
400 379 449 316 316
259 231 - - 126

8
techlibs/ice40/abc_lp.box
View File

@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
# Inputs: A B CI
# Inputs: A B I0 I3 CI
# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
$__ICE40_FULL_ADDER 1 1 3 2
589 558 465
675 609 186
$__ICE40_FULL_ADDER 1 1 5 2
589 558 661 465 465
675 609 - - 186

8
techlibs/ice40/abc_u.box
View File

@ -3,11 +3,11 @@
# NB: Inputs/Outputs must be ordered alphabetically
# (with exceptions for carry in/out)
# Inputs: A B CI
# Inputs: A B I0 I3 CI
# Outputs: O CO
# (NB: carry chain input/output must be last
# input/output and have been moved there
# overriding the alphabetical ordering)
$__ICE40_FULL_ADDER 1 1 3 2
1231 1205 874
675 609 278
$__ICE40_FULL_ADDER 1 1 5 2
1231 1205 1285 874 874
675 609 - - 278

19
techlibs/ice40/cells_sim.v
View File

@ -142,15 +142,16 @@ module SB_CARRY (output CO, input I0, I1, CI);
endmodule
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (
module \$__ICE40_CARRY_WRAPPER (
(* abc_carry *)
output CO,
output O,
input A,
input B,
input A, B,
(* abc_carry *)
input CI
input CI,
input I0, I3,
);
parameter LUT = 0;
SB_CARRY carry (
.I0(A),
.I1(B),
@ -158,16 +159,12 @@ module \$__ICE40_FULL_ADDER (
.CO(CO)
);
SB_LUT4 #(
// I0: 1010 1010 1010 1010
// I1: 1100 1100 1100 1100
// I2: 1111 0000 1111 0000
// I3: 1111 1111 0000 0000
.LUT_INIT(16'b 0110_1001_1001_0110)
.LUT_INIT(LUT)
) adder (
.I0(1'b0),
.I0(I0),
.I1(A),
.I2(B),
.I3(CI),
.I3(I3),
.O(O)
);
endmodule

45
techlibs/ice40/ice40_opt.cc
View File

@ -83,51 +83,6 @@ static void run_ice40_opts(Module *module)
}
continue;
}
if (cell->type == "$__ICE40_FULL_ADDER")
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
SigBit inbit[3] = {
cell->getPort("\\A"),
cell->getPort("\\B"),
cell->getPort("\\CI")
};
for (int i = 0; i < 3; i++)
if (inbit[i].wire == nullptr) {
if (inbit[i] == State::S1)
count_ones++;
else
count_zeros++;
} else
non_const_inputs.append(inbit[i]);
if (count_zeros >= 2)
replacement_output = State::S0;
else if (count_ones >= 2)
replacement_output = State::S1;
else if (GetSize(non_const_inputs) == 1)
replacement_output = non_const_inputs;
if (GetSize(replacement_output)) {
optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
module->connect(cell->getPort("\\CO")[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_FULL_ADDER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
cell->setPort("\\A", { State::S0, inbit[0], inbit[1], inbit[2] });
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B");
cell->unsetPort("\\CI");
cell->unsetPort("\\CO");
cell->unsetPort("\\O");
cell->setParam("\\LUT", RTLIL::Const::from_string("0110100110010110"));
cell->setParam("\\WIDTH", 4);
}
continue;
}
}
for (auto cell : sb_lut_cells)