mirror of https://github.com/YosysHQ/yosys.git
Remove -icells
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@ -230,9 +230,9 @@ struct SynthXilinxPass : public ScriptPass
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{
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if (check_label("begin")) {
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if (vpr)
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run("read_verilog -lib -icells -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
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run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
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else
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run("read_verilog -lib -icells +/xilinx/cells_sim.v");
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run("read_verilog -lib +/xilinx/cells_sim.v");
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run("read_verilog -lib +/xilinx/cells_xtra.v");
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