mirror of https://github.com/YosysHQ/yosys.git
synth_xilinx: cleanup help
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@ -530,7 +530,7 @@ struct SynthXilinxPass : public ScriptPass
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if (check_label("map_cells")) {
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// Needs to be done before logic optimization, so that inverters (OE vs T) are handled.
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if (help_mode || !noiopad)
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run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(only if not '-noiopad')");
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run("iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad $__XILINX_TOUTPAD OE:I:O -tinoutpad $__XILINX_TINOUTPAD OE:O:I:IO A:top", "(skip if '-noiopad')");
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std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
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if (widemux > 0)
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techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
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@ -593,17 +593,15 @@ struct SynthXilinxPass : public ScriptPass
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if (!nosrl || help_mode)
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run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
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std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
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if (help_mode)
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techmap_args += stringf("[-map %s]", ff_map_file.c_str());
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else if (!abc9)
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if (help_mode || !abc9)
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techmap_args += stringf(" -map %s", ff_map_file.c_str());
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run("techmap " + techmap_args, "(only if '-abc9')");
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run("techmap " + techmap_args);
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run("xilinx_dffopt");
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}
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if (check_label("finalize")) {
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if (help_mode || !noclkbuf)
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run("clkbufmap -buf BUFG O:I ", "(skip if '-noclkbuf')");
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run("clkbufmap -buf BUFG O:I", "(skip if '-noclkbuf')");
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if (help_mode || ise)
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run("extractinv -inv INV O:I", "(only if '-ise')");
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run("clean");
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