riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

xilinx: Add simulation models for IOBUF and OBUFT.

This commit is contained in:
Marcin Kościelnicki 2019-11-26 05:04:28 +01:00
parent 6cdea425b8
commit 0466c48533
3 changed files with 30 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
techlibs/xilinx/cells_sim.v
View File

@ -59,6 +59,34 @@ module OBUF(
assign O = I;
endmodule
module IOBUF (
(* iopad_external_pin *)
inout IO,
output O,
input I,
input T
);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
assign IO = T ? 1'bz : I;
assign O = IO;
endmodule
module OBUFT (
(* iopad_external_pin *)
output O,
input I,
input T
);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
assign O = T ? 1'bz : I;
endmodule
module BUFG(
(* clkbuf_driver *)
output O,

4
techlibs/xilinx/cells_xtra.py
View File

@ -326,7 +326,7 @@ CELLS = [
Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}),
# I/O.
Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
# Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}),
Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}),
@ -342,7 +342,7 @@ CELLS = [
Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
# Output + tristate.
Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
# Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}),
Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}),
# Pulls.
Cell('KEEPER'),

23
techlibs/xilinx/cells_xtra.v
View File

@ -8160,18 +8160,6 @@ module IBUFGDS_DIFF_OUT (...);
input IB;
endmodule
module IOBUF (...);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
(* iopad_external_pin *)
inout IO;
input I;
input T;
endmodule
module IOBUF_DCIEN (...);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
@ -8373,17 +8361,6 @@ module OBUFDS_DPHY (...);
input LPTX_T;
endmodule
module OBUFT (...);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
(* iopad_external_pin *)
output O;
input I;
input T;
endmodule
module OBUFTDS (...);
parameter CAPACITANCE = "DONT_CARE";
parameter IOSTANDARD = "DEFAULT";