mirror of https://github.com/YosysHQ/yosys.git
Move `techmap abc_map.v` into map_luts
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@ -380,7 +380,7 @@ struct SynthXilinxPass : public ScriptPass
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if (widemux > 0)
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techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
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if (abc9)
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techmap_args += " -map +/xilinx/ff_map.v -map +/xilinx/abc_map.v";
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techmap_args += " -map +/xilinx/ff_map.v";
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run("techmap " + techmap_args);
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run("clean");
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}
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@ -393,6 +393,7 @@ struct SynthXilinxPass : public ScriptPass
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if (family != "xc7")
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log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
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run("read_verilog -icells -lib +/xilinx/abc_model.v");
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run("techmap -map +/xilinx/abc_map.v";
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if (nowidelut)
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run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
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else
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