Missing wire declaration

2019-12-04 23:04:40 -08:00 · 2019-12-04 23:04:40 -08:00 · 0d248dd7ba
parent 19bc429482
commit 0d248dd7ba
1 changed files with 1 additions and 0 deletions
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@ -192,6 +192,7 @@ module FDCE (output Q, input C, CE, D, CLR);
 endmodule
 module FDCE_1 (output Q, input C, CE, D, CLR);
  parameter [0:0] INIT = 1'b0;
+  wire QQ, $nextQ, $abc9_currQ;
  generate if (INIT == 1'b1) begin
    assign Q = ~QQ;
    FDPE_1 #(