Merge branch 'master' into mwk/xilinx_bufgmap

2019-08-23 11:24:19 -07:00 · 2019-08-23 11:24:19 -07:00 · 20f4d191b5
parent 0d0ad15898 509c353fe9
commit 20f4d191b5
1 changed files with 1 additions and 1 deletions
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@ -343,7 +343,7 @@ module RAM64X1D (
  (* clkbuf_sink *)
  input  WCLK,
  (* abc_scc_break *)
-  input WE,
+  input  WE,
  input  A0, A1, A2, A3, A4, A5,
  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );