Forgot one

2019-08-23 11:23:50 -07:00 · 2019-08-23 11:23:50 -07:00 · 509c353fe9
parent a270af00cc
commit 509c353fe9
1 changed files with 2 additions and 1 deletions
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@ -325,7 +325,8 @@ module RAM64X1D (
  (* abc_scc_break *)
  input  D,
  input  WCLK,
-  (* abc_scc_break *) input WE,
+  (* abc_scc_break *)
+  input  WE,
  input  A0, A1, A2, A3, A4, A5,
  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );