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Merge branch 'master' into mwk/xilinx_bufgmap

This commit is contained in:
Eddie Hung 2019-08-23 11:23:31 -07:00
parent a0d85393e3 a270af00cc
commit 0d0ad15898
3 changed files with 36 additions and 18 deletions
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15
techlibs/ecp5/cells_sim.v
View File

@ -17,10 +17,12 @@ endmodule
// ---------------------------------------
(* abc_box_id=1, lib_whitebox *)
module CCU2C(
(* abc_carry *) input CIN,
(* abc_carry *)
input CIN,
input A0, B0, C0, D0, A1, B1, C1, D1,
output S0, S1,
(* abc_carry *) output COUT
(* abc_carry *)
output COUT
);
parameter [15:0] INIT0 = 16'h0000;
parameter [15:0] INIT1 = 16'h0000;
@ -109,9 +111,12 @@ endmodule
// ---------------------------------------
//(* abc_box_id=2 *)
module TRELLIS_DPR16X4 (
(* abc_scc_break *) input [3:0] DI,
(* abc_scc_break *) input [3:0] WAD,
(* abc_scc_break *) input WRE,
(* abc_scc_break *)
input [3:0] DI,
(* abc_scc_break *)
input [3:0] WAD,
(* abc_scc_break *)
input WRE,
input WCK,
input [3:0] RAD,
output [3:0] DO

6
techlibs/ice40/cells_sim.v
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@ -143,11 +143,13 @@ endmodule
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (
(* abc_carry *) output CO,
(* abc_carry *)
output CO,
output O,
input A,
input B,
(* abc_carry *) input CI
(* abc_carry *)
input CI
);
SB_CARRY carry (
.I0(A),

33
techlibs/xilinx/cells_sim.v
View File

@ -198,9 +198,11 @@ endmodule
(* abc_box_id = 4, lib_whitebox *)
module CARRY4(
(* abc_carry *) output [3:0] CO,
(* abc_carry *)
output [3:0] CO,
output [3:0] O,
(* abc_carry *) input CI,
(* abc_carry *)
input CI,
input CYINIT,
input [3:0] DI, S
);
@ -313,9 +315,12 @@ endmodule
(* abc_box_id = 5 *)
module RAM32X1D (
output DPO, SPO,
(* abc_scc_break *) input D,
(* clkbuf_sink *) input WCLK,
(* abc_scc_break *) input WE,
(* abc_scc_break *)
input D,
(* clkbuf_sink *)
input WCLK,
(* abc_scc_break *)
input WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
@ -333,9 +338,12 @@ endmodule
(* abc_box_id = 6 *)
module RAM64X1D (
output DPO, SPO,
(* abc_scc_break *) input D,
(* clkbuf_sink *) input WCLK,
(* abc_scc_break *) input WE,
(* abc_scc_break *)
input D,
(* clkbuf_sink *)
input WCLK,
(* abc_scc_break *)
input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
@ -353,9 +361,12 @@ endmodule
(* abc_box_id = 7 *)
module RAM128X1D (
output DPO, SPO,
(* abc_scc_break *) input D,
(* clkbuf_sink *) input WCLK,
(* abc_scc_break *) input WE,
(* abc_scc_break *)
input D,
(* clkbuf_sink *)
input WCLK,
(* abc_scc_break *)
input WE,
input [6:0] A, DPRA
);
parameter INIT = 128'h0;