mirror of https://github.com/YosysHQ/yosys.git
Do not drop async control signals in abc_map.v
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@ -120,10 +120,11 @@ module FDCE (output reg Q, input C, CE, D, CLR);
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_CLR_INVERTED(IS_CLR_INVERTED)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(IS_CLR_INVERTED)
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.D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
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// ^^^ Note that async
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// control is disabled
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// here but captured by
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// control is not directly
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// supported by abc9 but its
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// behaviour is captured by
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// $__ABC9_ASYNC below
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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@ -142,10 +143,11 @@ module FDCE_1 (output reg Q, input C, CE, D, CLR);
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FDCE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(1'b0)
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.D(D), .Q($nextQ), .C(C), .CE(CE), .CLR(CLR)
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// ^^^ Note that async
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// control is disabled
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// here but captured by
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// control is not directly
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// supported by abc9 but its
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// behaviour is captured by
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// $__ABC9_ASYNC below
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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@ -169,10 +171,11 @@ module FDPE (output reg Q, input C, CE, D, PRE);
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_PRE_INVERTED(IS_PRE_INVERTED),
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(IS_PRE_INVERTED)
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.D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
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// ^^^ Note that async
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// control is disabled
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// here but captured by
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// control is not directly
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// supported by abc9 but its
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// behaviour is captured by
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// $__ABC9_ASYNC below
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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@ -189,10 +192,11 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
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FDPE_1 #(
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.INIT(INIT)
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) _TECHMAP_REPLACE_ (
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.D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(1'b0)
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.D(D), .Q($nextQ), .C(C), .CE(CE), .PRE(PRE)
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// ^^^ Note that async
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// control is disabled
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// here but captured by
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// control is not directly
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// supported by abc9 but its
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// behaviour is captured by
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// $__ABC9_ASYNC below
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);
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\$__ABC9_FF_ abc_dff (.D($nextQ), .Q($abc9_currQ));
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