mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
ice40: Support for post-place-and-route timing simulations
This commit is contained in:
Clifford Wolf
GitHub
commit
056ef76711
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@ -1,4 +1,4 @@
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`timescale 1ps / 1ps
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`define SB_DFF_REG reg Q = 0
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// `define SB_DFF_REG reg Q
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@ -81,6 +81,37 @@ module SB_IO (
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if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
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endgenerate
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`endif
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`ifdef TIMING
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specify
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(INPUT_CLK => D_IN_0) = (0:0:0, 0:0:0);
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(INPUT_CLK => D_IN_1) = (0:0:0, 0:0:0);
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(PACKAGE_PIN => D_IN_0) = (0:0:0, 0:0:0);
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(OUTPUT_CLK => PACKAGE_PIN) = (0:0:0, 0:0:0);
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(D_OUT_0 => PACKAGE_PIN) = (0:0:0, 0:0:0);
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(OUTPUT_ENABLE => PACKAGE_PIN) = (0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
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$setuphold(posedge INPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
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$setuphold(posedge INPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
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$setuphold(posedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
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$setuphold(posedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
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$setuphold(negedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
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$setuphold(negedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
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endspecify
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`endif
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endmodule
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module SB_GB_IO (
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@ -127,6 +158,11 @@ module SB_GB (
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output GLOBAL_BUFFER_OUTPUT
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);
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assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
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`ifdef TIMING
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specify
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(USER_SIGNAL_TO_GLOBAL_BUFFER => GLOBAL_BUFFER_OUTPUT) = (0:0:0, 0:0:0);
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endspecify
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`endif
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endmodule
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// SiliconBlue Logic Cells
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@ -830,33 +866,81 @@ module ICESTORM_LC (
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parameter [0:0] CIN_CONST = 0;
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parameter [0:0] CIN_SET = 0;
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wire I0_pd = (I0 === 1'bz) ? 1'b0 : I0;
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wire I1_pd = (I1 === 1'bz) ? 1'b0 : I1;
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wire I2_pd = (I2 === 1'bz) ? 1'b0 : I2;
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wire I3_pd = (I3 === 1'bz) ? 1'b0 : I3;
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wire SR_pd = (SR === 1'bz) ? 1'b0 : SR;
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wire CEN_pu = (CEN === 1'bz) ? 1'b1 : CEN;
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wire mux_cin = CIN_CONST ? CIN_SET : CIN;
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assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
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assign COUT = CARRY_ENABLE ? (I1_pd && I2_pd) || ((I1_pd || I2_pd) && mux_cin) : 1'bx;
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wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
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wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];
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wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0];
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wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0];
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wire [7:0] lut_s3 = I3_pd ? LUT_INIT[15:8] : LUT_INIT[7:0];
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wire [3:0] lut_s2 = I2_pd ? lut_s3[ 7:4] : lut_s3[3:0];
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wire [1:0] lut_s1 = I1_pd ? lut_s2[ 3:2] : lut_s2[1:0];
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wire lut_o = I0_pd ? lut_s1[ 1] : lut_s1[ 0];
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assign LO = lut_o;
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wire polarized_clk;
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assign polarized_clk = CLK ^ NEG_CLK;
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reg o_reg;
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reg o_reg = 1'b0;
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always @(posedge polarized_clk)
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if (CEN)
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o_reg <= SR ? SET_NORESET : lut_o;
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if (CEN_pu)
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o_reg <= SR_pd ? SET_NORESET : lut_o;
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reg o_reg_async;
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reg o_reg_async = 1'b0;
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always @(posedge polarized_clk, posedge SR)
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if (SR)
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o_reg <= SET_NORESET;
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else if (CEN)
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o_reg <= lut_o;
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if (SR_pd)
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o_reg_async <= SET_NORESET;
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else if (CEN_pu)
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o_reg_async <= lut_o;
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assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
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`ifdef TIMING
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specify
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(I0 => O) = (0:0:0, 0:0:0);
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(I1 => O) = (0:0:0, 0:0:0);
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(I2 => O) = (0:0:0, 0:0:0);
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(I3 => O) = (0:0:0, 0:0:0);
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(I0 => LO) = (0:0:0, 0:0:0);
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(I1 => LO) = (0:0:0, 0:0:0);
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(I2 => LO) = (0:0:0, 0:0:0);
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(I3 => LO) = (0:0:0, 0:0:0);
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(I1 => COUT) = (0:0:0, 0:0:0);
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(I2 => COUT) = (0:0:0, 0:0:0);
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(CIN => COUT) = (0:0:0, 0:0:0);
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(CLK => O) = (0:0:0, 0:0:0);
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(SR => O) = (0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge I0, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge I0, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge I0, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge I0, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge I1, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge I1, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge I1, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge I1, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge I2, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge I2, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge I2, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge I2, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge I3, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge I3, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge I3, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge I3, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge CEN, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge CEN, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge SR, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge SR, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge SR, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge SR, 0:0:0, 0:0:0);
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endspecify
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`endif
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endmodule
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// SiliconBlue PLL Cells
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@ -1576,3 +1660,341 @@ module SB_MAC16 (
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assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
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assign O = {Oh, Ol};
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endmodule
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// Post-place-and-route RAM model
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module ICESTORM_RAM(
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output RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0,
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input RCLK, RCLKE, RE,
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input RADDR_10, RADDR_9, RADDR_8, RADDR_7, RADDR_6, RADDR_5, RADDR_4, RADDR_3, RADDR_2, RADDR_1, RADDR_0,
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input WCLK, WCLKE, WE,
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input WADDR_10, WADDR_9, WADDR_8, WADDR_7, WADDR_6, WADDR_5, WADDR_4, WADDR_3, WADDR_2, WADDR_1, WADDR_0,
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input MASK_15, MASK_14, MASK_13, MASK_12, MASK_11, MASK_10, MASK_9, MASK_8, MASK_7, MASK_6, MASK_5, MASK_4, MASK_3, MASK_2, MASK_1, MASK_0,
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input WDATA_15, WDATA_14, WDATA_13, WDATA_12, WDATA_11, WDATA_10, WDATA_9, WDATA_8, WDATA_7, WDATA_6, WDATA_5, WDATA_4, WDATA_3, WDATA_2, WDATA_1, WDATA_0
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);
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parameter WRITE_MODE = 0;
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parameter READ_MODE = 0;
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parameter NEG_CLK_R = 1'b0;
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parameter NEG_CLK_W = 1'b0;
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parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
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// Pull-down and pull-up functions
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function pd;
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input x;
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begin
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pd = (x === 1'bz) ? 1'b0 : x;
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end
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endfunction
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function pu;
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input x;
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begin
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pu = (x === 1'bz) ? 1'b1 : x;
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end
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endfunction
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SB_RAM40_4K #(
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.WRITE_MODE(WRITE_MODE),
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.READ_MODE (READ_MODE ),
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.INIT_0 (INIT_0 ),
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.INIT_1 (INIT_1 ),
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.INIT_2 (INIT_2 ),
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.INIT_3 (INIT_3 ),
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.INIT_4 (INIT_4 ),
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.INIT_5 (INIT_5 ),
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.INIT_6 (INIT_6 ),
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.INIT_7 (INIT_7 ),
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.INIT_8 (INIT_8 ),
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.INIT_9 (INIT_9 ),
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.INIT_A (INIT_A ),
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.INIT_B (INIT_B ),
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.INIT_C (INIT_C ),
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.INIT_D (INIT_D ),
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.INIT_E (INIT_E ),
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.INIT_F (INIT_F )
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) RAM (
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.RDATA({RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0}),
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.RCLK (pd(RCLK) ^ NEG_CLK_R),
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.RCLKE(pu(RCLKE)),
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.RE (pd(RE)),
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.RADDR({pd(RADDR_10), pd(RADDR_9), pd(RADDR_8), pd(RADDR_7), pd(RADDR_6), pd(RADDR_5), pd(RADDR_4), pd(RADDR_3), pd(RADDR_2), pd(RADDR_1), pd(RADDR_0)}),
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.WCLK (pd(WCLK) ^ NEG_CLK_W),
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.WCLKE(pu(WCLKE)),
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.WE (pd(WE)),
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.WADDR({pd(WADDR_10), pd(WADDR_9), pd(WADDR_8), pd(WADDR_7), pd(WADDR_6), pd(WADDR_5), pd(WADDR_4), pd(WADDR_3), pd(WADDR_2), pd(WADDR_1), pd(WADDR_0)}),
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.MASK ({pd(MASK_15), pd(MASK_14), pd(MASK_13), pd(MASK_12), pd(MASK_11), pd(MASK_10), pd(MASK_9), pd(MASK_8),
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pd(MASK_7), pd(MASK_6), pd(MASK_5), pd(MASK_4), pd(MASK_3), pd(MASK_2), pd(MASK_1), pd(MASK_0)}),
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.WDATA({pd(WDATA_15), pd(WDATA_14), pd(WDATA_13), pd(WDATA_12), pd(WDATA_11), pd(WDATA_10), pd(WDATA_9), pd(WDATA_8),
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pd(WDATA_7), pd(WDATA_6), pd(WDATA_5), pd(WDATA_4), pd(WDATA_3), pd(WDATA_2), pd(WDATA_1), pd(WDATA_0)})
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);
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`ifdef TIMING
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specify
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(RCLK => RDATA_15) = (0:0:0, 0:0:0);
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(RCLK => RDATA_14) = (0:0:0, 0:0:0);
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(RCLK => RDATA_13) = (0:0:0, 0:0:0);
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(RCLK => RDATA_12) = (0:0:0, 0:0:0);
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(RCLK => RDATA_11) = (0:0:0, 0:0:0);
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(RCLK => RDATA_10) = (0:0:0, 0:0:0);
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(RCLK => RDATA_9) = (0:0:0, 0:0:0);
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(RCLK => RDATA_8) = (0:0:0, 0:0:0);
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(RCLK => RDATA_7) = (0:0:0, 0:0:0);
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(RCLK => RDATA_6) = (0:0:0, 0:0:0);
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(RCLK => RDATA_5) = (0:0:0, 0:0:0);
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(RCLK => RDATA_4) = (0:0:0, 0:0:0);
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(RCLK => RDATA_3) = (0:0:0, 0:0:0);
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(RCLK => RDATA_2) = (0:0:0, 0:0:0);
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(RCLK => RDATA_1) = (0:0:0, 0:0:0);
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(RCLK => RDATA_0) = (0:0:0, 0:0:0);
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$setuphold(posedge RCLK, posedge RCLKE, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, negedge RCLKE, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, posedge RCLKE, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, negedge RCLKE, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, posedge RE, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, negedge RE, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, posedge RE, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, negedge RE, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0);
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$setuphold(negedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0);
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$setuphold(posedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WCLKE, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WCLKE, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WCLKE, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WCLKE, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WE, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WE, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WE, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WE, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_15, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_15, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_15, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_15, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_14, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_14, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_14, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_14, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_13, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_13, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_13, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_13, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_12, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_12, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_12, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_12, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_11, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_11, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_11, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_11, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_10, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_10, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_10, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_10, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_9, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_9, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_9, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_9, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_8, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_8, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_8, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_8, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_7, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_7, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_7, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_7, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_6, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_6, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_6, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_6, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_5, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_5, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_5, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_5, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_4, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_4, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_4, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_4, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_3, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_3, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_3, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_3, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_2, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_2, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_2, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_2, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_1, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_1, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_1, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_1, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge MASK_0, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge MASK_0, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge MASK_0, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge MASK_0, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0);
|
||||
$setuphold(posedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0);
|
||||
$setuphold(negedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0);
|
||||
|
||||
endspecify
|
||||
`endif
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue