mirror of https://github.com/YosysHQ/yosys.git
parent
1784d25f53
commit
95c46ccc55
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@ -27,6 +27,7 @@ techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt))
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@ -438,7 +438,12 @@ struct SynthXilinxPass : public ScriptPass
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run("memory_bram -rules +/xilinx/{family}_brams.txt");
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run("techmap -map +/xilinx/{family}_brams_map.v");
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} else if (!nobram) {
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if (family == "xc6s") {
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if (family == "xc3sda") {
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// Supported block RAMs for Spartan 3A DSP are
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// a subset of Spartan 6's ones.
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run("memory_bram -rules +/xilinx/xc3sda_brams.txt");
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run("techmap -map +/xilinx/xc6s_brams_map.v");
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} else if (family == "xc6s") {
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run("memory_bram -rules +/xilinx/xc6s_brams.txt");
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run("techmap -map +/xilinx/xc6s_brams_map.v");
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} else if (family == "xc6v" || family == "xc7") {
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@ -0,0 +1,32 @@
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bram $__XILINX_RAMB16BWER_TDP
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init 1
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abits 9 @a9d36
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dbits 36 @a9d36
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abits 10 @a10d18
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dbits 18 @a10d18
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abits 11 @a11d9
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dbits 9 @a11d9
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abits 12 @a12d4
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dbits 4 @a12d4
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abits 13 @a13d2
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dbits 2 @a13d2
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abits 14 @a14d1
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dbits 1 @a14d1
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 4 @a9d36
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enable 1 2 @a10d18
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enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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match $__XILINX_RAMB16BWER_TDP
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min bits 4096
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min efficiency 5
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shuffle_enable B
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make_transp
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endmatch
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