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Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
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@ -380,9 +380,10 @@ endmodule
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module SRL16E (
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output Q,
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input A0, A1, A2, A3, CE,
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(* clkbuf_sink *)
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input CLK,
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input A0, A1, A2, A3, CE, D
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input D
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);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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@ -401,7 +402,10 @@ endmodule
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module SRLC16E (
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output Q,
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output Q15,
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input A0, A1, A2, A3, CE, CLK, D
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input A0, A1, A2, A3, CE,
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(* clkbuf_sink *)
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input CLK,
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input D
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);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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@ -422,9 +426,10 @@ module SRLC32E (
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output Q,
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output Q31,
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input [4:0] A,
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input CE,
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(* clkbuf_sink *)
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input CLK,
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input CE, D
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input D
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);
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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