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Panic over. Model was elsewhere. Re-arrange for consistency

This commit is contained in:
Eddie Hung 2019-10-04 10:48:44 -07:00
parent 4e11782cde
commit 9fef1df3c1
5 changed files with 4 additions and 31 deletions
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1
techlibs/ecp5/synth_ecp5.cc
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@ -311,6 +311,7 @@ struct SynthEcp5Pass : public ScriptPass
run("techmap " + techmap_args);
if (abc9) {
run("read_verilog -icells -lib +/ecp5/abc_model.v");
if (nowidelut)
run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
else

1
techlibs/ice40/Makefile.inc
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@ -28,6 +28,7 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_model.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))

2
techlibs/ice40/abc_model.v
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@ -25,5 +25,3 @@ module \$__ICE40_CARRY_WRAPPER (
.O(O)
);
endmodule

28
techlibs/ice40/cells_sim.v
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@ -145,34 +145,6 @@ module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_CARRY_WRAPPER (
(* abc_carry *)
output CO,
output O,
input A, B,
(* abc_carry *)
input CI,
input I0, I3
);
parameter LUT = 0;
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
SB_LUT4 #(
.LUT_INIT(LUT)
) adder (
.I0(I0),
.I1(A),
.I2(B),
.I3(I3),
.O(O)
);
endmodule
// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102

3
techlibs/ice40/synth_ice40.cc
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@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass
define = "-D ICE40_U";
else
define = "-D ICE40_HX";
run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
@ -349,6 +349,7 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc == "abc9") {
run("read_verilog -icells -lib +/ice40/abc_model.v");
int wire_delay;
if (device_opt == "lp")
wire_delay = 400;