mirror of https://github.com/YosysHQ/yosys.git
add MUX support
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@ -5,6 +5,9 @@ module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D),
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module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
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module \$__DFFS_PP1_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
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module \$_MUX_ (input A, B, S, output Y); MUX2 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule
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module \$_MUX4_ (input A, B, C, D, S, T, output Y); MUX4 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .I2(C), .I3(D), .S0(S), .S1(T), .O(Y)); endmodule
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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@ -24,6 +24,19 @@ module LUT4(output F, input I0, I1, I2, I3);
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assign F = I0 ? s1[1] : s1[0];
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endmodule
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module MUX2 (I0, I1, S0, O);
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input I0, I1, S0;
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output O;
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assign O = S0 ? I1 : I0;
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endmodule
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module MUX4 (I0, I1, I2, I3, S0, S1, O);
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input I0, I1, I2, I3, S0, S1;
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output O;
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assign O = S1 ? (S0 ? I3 : I2) :
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(S0 ? I1 : I0);
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endmodule
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module DFF (output reg Q, input CLK, D);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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@ -196,6 +196,7 @@ struct SynthGowinPass : public ScriptPass
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run("opt_clean");
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if (!nodffe)
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run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
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run("muxcover -mux4");
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run("techmap -map +/gowin/cells_map.v");
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run("opt_expr -mux_undef");
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run("simplemap");
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