mirror of https://github.com/YosysHQ/yosys.git
ice40: Support for post-pnr timing simulation
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
parent
f2aa2d1bb4
commit
37dd3ad3fe
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@ -1,4 +1,4 @@
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`timescale 1ps / 1ps
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`define SB_DFF_REG reg Q = 0
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// `define SB_DFF_REG reg Q
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@ -81,6 +81,37 @@ module SB_IO (
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if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
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endgenerate
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`endif
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`ifdef TIMING
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specify
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(INPUT_CLK => D_IN_0) = (0:0:0, 0:0:0);
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(INPUT_CLK => D_IN_1) = (0:0:0, 0:0:0);
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(PACKAGE_PIN => D_IN_0) = (0:0:0, 0:0:0);
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(OUTPUT_CLK => PACKAGE_PIN) = (0:0:0, 0:0:0);
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(D_OUT_0 => PACKAGE_PIN) = (0:0:0, 0:0:0);
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(OUTPUT_ENABLE => PACKAGE_PIN) = (0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
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$setuphold(posedge INPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
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$setuphold(posedge INPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
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$setuphold(posedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
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$setuphold(posedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
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$setuphold(negedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
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$setuphold(negedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
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$setuphold(posedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
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$setuphold(negedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
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endspecify
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`endif
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endmodule
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module SB_GB_IO (
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@ -127,6 +158,11 @@ module SB_GB (
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output GLOBAL_BUFFER_OUTPUT
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);
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assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
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`ifdef TIMING
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specify
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(USER_SIGNAL_TO_GLOBAL_BUFFER => GLOBAL_BUFFER_OUTPUT) = (0:0:0, 0:0:0);
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endspecify
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`endif
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endmodule
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// SiliconBlue Logic Cells
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@ -830,33 +866,81 @@ module ICESTORM_LC (
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parameter [0:0] CIN_CONST = 0;
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parameter [0:0] CIN_SET = 0;
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wire I0_pd = (I0 === 1'bz) ? 1'b0 : I0;
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wire I1_pd = (I1 === 1'bz) ? 1'b0 : I1;
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wire I2_pd = (I2 === 1'bz) ? 1'b0 : I2;
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wire I3_pd = (I3 === 1'bz) ? 1'b0 : I3;
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wire SR_pd = (SR === 1'bz) ? 1'b0 : SR;
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wire CEN_pu = (CEN === 1'bz) ? 1'b1 : CEN;
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wire mux_cin = CIN_CONST ? CIN_SET : CIN;
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assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
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assign COUT = CARRY_ENABLE ? (I1_pd && I2_pd) || ((I1_pd || I2_pd) && mux_cin) : 1'bx;
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wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
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wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];
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wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0];
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wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0];
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wire [7:0] lut_s3 = I3_pd ? LUT_INIT[15:8] : LUT_INIT[7:0];
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wire [3:0] lut_s2 = I2_pd ? lut_s3[ 7:4] : lut_s3[3:0];
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wire [1:0] lut_s1 = I1_pd ? lut_s2[ 3:2] : lut_s2[1:0];
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wire lut_o = I0_pd ? lut_s1[ 1] : lut_s1[ 0];
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assign LO = lut_o;
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wire polarized_clk;
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assign polarized_clk = CLK ^ NEG_CLK;
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reg o_reg;
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reg o_reg = 1'b0;
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always @(posedge polarized_clk)
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if (CEN)
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o_reg <= SR ? SET_NORESET : lut_o;
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if (CEN_pu)
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o_reg <= SR_pd ? SET_NORESET : lut_o;
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reg o_reg_async;
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reg o_reg_async = 1'b0;
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always @(posedge polarized_clk, posedge SR)
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if (SR)
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if (SR_pd)
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o_reg <= SET_NORESET;
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else if (CEN)
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else if (CEN_pu)
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o_reg <= lut_o;
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assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
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`ifdef TIMING
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specify
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(I0 => O) = (0:0:0, 0:0:0);
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(I1 => O) = (0:0:0, 0:0:0);
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(I2 => O) = (0:0:0, 0:0:0);
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(I3 => O) = (0:0:0, 0:0:0);
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(I0 => LO) = (0:0:0, 0:0:0);
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(I1 => LO) = (0:0:0, 0:0:0);
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(I2 => LO) = (0:0:0, 0:0:0);
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(I3 => LO) = (0:0:0, 0:0:0);
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(I1 => COUT) = (0:0:0, 0:0:0);
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(I2 => COUT) = (0:0:0, 0:0:0);
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(CIN => COUT) = (0:0:0, 0:0:0);
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(CLK => O) = (0:0:0, 0:0:0);
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(SR => O) = (0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge I0, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge I0, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge I0, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge I0, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge I1, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge I1, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge I1, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge I1, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge I2, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge I2, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge I2, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge I2, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge I3, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge I3, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge I3, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge I3, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge CEN, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge CEN, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, posedge SR, 0:0:0, 0:0:0);
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$setuphold(posedge CLK, negedge SR, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, posedge SR, 0:0:0, 0:0:0);
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$setuphold(negedge CLK, negedge SR, 0:0:0, 0:0:0);
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endspecify
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`endif
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endmodule
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// SiliconBlue PLL Cells
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