mirror of https://github.com/YosysHQ/yosys.git
add wide luts
This commit is contained in:
Pepijn de Vos
parent
5fad53b504
commit
f88335a8a5
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@ -101,6 +101,30 @@ module \$lut (A, Y);
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if (WIDTH == 4) begin
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LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
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end else
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if (WIDTH == 5) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[1:4]), .Y(f0));
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\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[1:4]), .Y(f1));
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MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
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end else
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if (WIDTH == 6) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[1:5]), .Y(f0));
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\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[1:5]), .Y(f1));
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MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
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end else
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if (WIDTH == 7) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[1:6]), .Y(f0));
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\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[1:6]), .Y(f1));
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MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
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end else
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if (WIDTH == 8) begin
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wire f0, f1;
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\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[1:7]), .Y(f0));
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\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[1:7]), .Y(f1));
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MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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@ -24,6 +24,41 @@ module LUT4(output F, input I0, I1, I2, I3);
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assign F = I0 ? s1[1] : s1[0];
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endmodule
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module MUX2 (O, I0, I1, S0);
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input I0,I1;
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input S0;
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output O;
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assign O = S0 ? I1 : I0;
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endmodule
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module MUX2_LUT5 (O, I0, I1, S0);
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input I0,I1;
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input S0;
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output O;
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MUX2 mux2_lut5 (O, I0, I1, S0);
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endmodule
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module MUX2_LUT6 (O, I0, I1, S0);
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input I0,I1;
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input S0;
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output O;
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MUX2 mux2_lut6 (O, I0, I1, S0);
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endmodule
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module MUX2_LUT7 (O, I0, I1, S0);
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input I0,I1;
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input S0;
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output O;
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MUX2 mux2_lut7 (O, I0, I1, S0);
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endmodule
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module MUX2_LUT8 (O, I0, I1, S0);
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input I0,I1;
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input S0;
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output O;
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MUX2 mux2_lut8 (O, I0, I1, S0);
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endmodule
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module DFF (output reg Q, input CLK, D);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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@ -1,19 +1,19 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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@ -31,38 +31,44 @@ struct SynthGowinPass : public ScriptPass
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_gowin [options]\n");
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log(" synth_gowin [options]\n");
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log("\n");
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log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -vout <file>\n");
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log(" write the design to the specified Verilog netlist file. writing of an\n");
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log(" output file is omitted if this parameter is not specified.\n");
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log(" -vout <file>\n");
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log(" write the design to the specified Verilog netlist file. writing of an\n");
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log(" output file is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -nodffe\n");
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log(" do not use flipflops with CE in output netlist\n");
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log(" -nodffe\n");
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log(" do not use flipflops with CE in output netlist\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use BRAM cells in output netlist\n");
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log(" -nobram\n");
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log(" do not use BRAM cells in output netlist\n");
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log("\n");
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log(" -nodram\n");
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log(" do not use distributed RAM cells in output netlist\n");
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log(" -nodram\n");
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log(" do not use distributed RAM cells in output netlist\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log(" -nowidelut\n");
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log(" do not use muxes to implement LUTs larger than LUT4s\n");
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log("\n");
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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@ -71,7 +77,7 @@ struct SynthGowinPass : public ScriptPass
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}
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string top_opt, vout_file;
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bool retime, nobram, nodram, flatten, nodffe;
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bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9;
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void clear_flags() YS_OVERRIDE
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{
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@ -82,6 +88,8 @@ struct SynthGowinPass : public ScriptPass
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nobram = false;
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nodffe = false;
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nodram = false;
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nowidelut = false;
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abc9 = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -128,6 +136,14 @@ struct SynthGowinPass : public ScriptPass
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flatten = false;
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continue;
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}
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if (args[argidx] == "-nowidelut") {
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nowidelut = true;
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc9 = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -164,7 +180,7 @@ struct SynthGowinPass : public ScriptPass
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run("synth -run coarse");
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}
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if (!nobram && check_label("bram", "(skip if -nobram)"))
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if (!nobram && check_label("bram", "(skip if -nobram)"))
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{
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run("memory_bram -rules +/gowin/bram.txt");
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run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
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@ -203,7 +219,15 @@ struct SynthGowinPass : public ScriptPass
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if (check_label("map_luts"))
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{
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run("abc -lut 4");
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if (nowidelut && abc9) {
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run("abc9 -lut 4");
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} else if (nowidelut && !abc9) {
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run("abc -lut 4");
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} else if (!nowidelut && abc9) {
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run("abc9 -lut 4:8");
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} else if (!nowidelut && !abc9) {
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run("abc -lut 4:8");
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}
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run("clean");
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}
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