Eddie Hung
89359b6927
Missing dep for test_pmgen
2019-08-30 14:00:40 -07:00
Eddie Hung
723815b384
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-30 13:26:19 -07:00
Eddie Hung
c7f1ccbcb0
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 12:28:35 -07:00
Eddie Hung
999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
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abc9 to not call "clean" at end of run (often called outside)
2019-08-30 12:27:09 -07:00
Eddie Hung
c1459bc748
Do not restrict multiplier to unsigned
2019-08-30 12:22:14 -07:00
Eddie Hung
4e782f1509
New pmgen requires explicit accept
2019-08-30 11:02:10 -07:00
Eddie Hung
d2d2816f8c
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-30 10:30:54 -07:00
Eddie Hung
f0fef90e9d
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 10:30:46 -07:00
Eddie Hung
295c18bd6b
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-08-30 09:50:20 -07:00
Eddie Hung
6e475484b2
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-30 09:37:32 -07:00
David Shah
6919c0f9b0
Merge branch 'master' into xc7dsp
2019-08-30 13:57:15 +01:00
Eddie Hung
18cabe9370
Output has priority over input when stitching in abc9
2019-08-29 17:24:03 -07:00
Eddie Hung
3e0f73c3df
abc9 to not call "clean" at end of run (often called outside)
2019-08-29 12:12:59 -07:00
Eddie Hung
1467761060
Fix typo that's gone unnoticed for 5 months!?!
2019-08-29 10:33:28 -07:00
Eddie Hung
c4e5310823
Use a dummy box file if none specified
2019-08-28 20:58:55 -07:00
Eddie Hung
116c249601
-auto-top should check $abstract (deferred) modules with (* top *)
2019-08-28 19:59:25 -07:00
Eddie Hung
4eb5847dbd
Cleanup
2019-08-28 18:10:33 -07:00
Eddie Hung
0af64df10c
Account for D port being a constant
2019-08-28 15:32:38 -07:00
Eddie Hung
a45c09c8d1
Account for D port being a constant
2019-08-28 15:31:55 -07:00
Eddie Hung
1b08f861b6
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-28 15:31:48 -07:00
Eddie Hung
8d820a9884
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-28 15:19:10 -07:00
Eddie Hung
fc727fa5c9
Merge pull request #1334 from YosysHQ/clifford/async2synclatch
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Add $dlatch support to async2sync
2019-08-28 12:36:06 -07:00
Eddie Hung
52c4655de3
No need to replace Q of slice since $shiftx is autoremove-d
2019-08-28 11:06:11 -07:00
Eddie Hung
11e3eb1009
More cleanup
2019-08-28 10:19:35 -07:00
Eddie Hung
86b538bd02
More cleanup
2019-08-28 10:11:09 -07:00
Eddie Hung
c4d1bd988b
Do not use default_params dict, hardcode default values, cleanup
2019-08-28 10:06:40 -07:00
Eddie Hung
c3e9627afe
Always generate if no match
2019-08-28 09:54:56 -07:00
Eddie Hung
0ebe2c9831
Rename test_pmgen arg xilinx_srl.{fixed,variable}
2019-08-28 09:27:03 -07:00
Eddie Hung
ba5d81c7f1
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-28 09:21:03 -07:00
Clifford Wolf
47ffbf554e
Fix typo
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:06:42 +02:00
Clifford Wolf
0fda0e821c
Add "paramap" pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:03:27 +02:00
Clifford Wolf
c499dc3e73
Add $dlatch support to async2sync
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 09:45:22 +02:00
Clifford Wolf
70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init
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In sat: 'x' in init attr should be ignored
2019-08-28 00:18:14 +02:00
Eddie Hung
28133432be
Ignore all 1'bx in (* init *)
2019-08-27 09:24:59 -07:00
Marcin Kościelnicki
5fb4b12cb5
improve clkbuf_inhibit propagation upwards through hierarchy
2019-08-27 17:26:47 +02:00
Eddie Hung
9172d4a674
Missing close bracket
2019-08-26 21:02:52 -07:00
Eddie Hung
6b5e65919a
Revert "In sat: 'x' in init attr should not override constant"
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This reverts commit 2b37a093e9
.
2019-08-26 17:52:57 -07:00
Eddie Hung
54422c5bb4
Remove leftover header
2019-08-26 17:51:13 -07:00
Eddie Hung
e95fb24574
Improve xilinx_srl.fixed generate, add .variable generate
2019-08-26 17:49:08 -07:00
Eddie Hung
45c34c87ee
Account for maxsubcnt overflowing
2019-08-26 17:48:54 -07:00
Eddie Hung
b32d6bf403
Add xilinx_srl_pm.variable to test_pmgen
2019-08-26 17:44:57 -07:00
Eddie Hung
e574edc3e9
Populate generate for xilinx_srl.fixed pattern
2019-08-26 14:21:17 -07:00
Eddie Hung
cf9e017127
Add xilinx_srl_fixed, fix typos
2019-08-26 14:20:06 -07:00
Eddie Hung
a098205479
Merge branch 'master' into mwk/xilinx_bufgmap
2019-08-26 13:25:17 -07:00
Eddie Hung
7911143827
Create new $__XILINX_SHREG_ cell for variable length too
2019-08-23 18:15:49 -07:00
Eddie Hung
a048fc93e8
Do not allow Q of last cell of variable length SRL to be (* keep *)
2019-08-23 18:15:24 -07:00
Eddie Hung
ee9f6e6243
Also add first.Q to chain_bits since variable length
2019-08-23 18:14:06 -07:00
Eddie Hung
70ce3d0670
Do not enforce !EN_POLARITY on $dffe
2019-08-23 18:11:28 -07:00
Eddie Hung
188b49378a
Create new cell for fixed length SRL
2019-08-23 17:25:30 -07:00
Eddie Hung
e081303ee8
Cleanup FDRE matching
2019-08-23 17:23:52 -07:00
Eddie Hung
54488cfb82
Oops don't need a finally block
2019-08-23 16:39:37 -07:00
Eddie Hung
83e2d87fb8
Keep track of bits in variable length chain, to check for taps
2019-08-23 16:21:10 -07:00
Eddie Hung
f2d4814284
Don't forget $dff has no EN
2019-08-23 16:14:57 -07:00
Eddie Hung
2217d926a9
Same for variable length
2019-08-23 16:13:16 -07:00
Eddie Hung
b1caf7be5e
Filter on en_port for fixed length
2019-08-23 16:09:46 -07:00
Eddie Hung
513af10d77
Check clock is consistent
2019-08-23 15:18:26 -07:00
Eddie Hung
c762618783
Fix last_cell.D
2019-08-23 15:08:49 -07:00
Eddie Hung
ca5de78e76
Revert "Add a unique argument to pmgen's nusers()"
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This reverts commit 1d88887cfd
.
2019-08-23 15:04:00 -07:00
Eddie Hung
e85e6e8d45
Revert "Fix polarity"
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This reverts commit 9cd23cf0fe
.
2019-08-23 15:03:42 -07:00
Eddie Hung
9cd23cf0fe
Fix polarity
2019-08-23 14:49:34 -07:00
Eddie Hung
c2757613b6
Check for non unique nusers/fanouts
2019-08-23 14:32:36 -07:00
Eddie Hung
1d88887cfd
Add a unique argument to pmgen's nusers()
2019-08-23 14:32:17 -07:00
Eddie Hung
8ecfd55d5a
Update doc
2019-08-23 14:16:41 -07:00
Eddie Hung
3d7f4aa0c8
Remove (* init *) entry when consumed into SRL
2019-08-23 13:56:01 -07:00
Eddie Hung
48c424e45b
Cleanup
2019-08-23 13:46:05 -07:00
Eddie Hung
967a36c125
indo -> into
2019-08-23 13:16:50 -07:00
Eddie Hung
a1f78eab04
indo -> into
2019-08-23 13:15:41 -07:00
Eddie Hung
5939ffdc07
Forgot to slice
2019-08-23 13:06:59 -07:00
Eddie Hung
242b3083ea
Cope with possibility that D could connect to Q on same cell
2019-08-23 13:06:31 -07:00
Eddie Hung
18b64609c2
xilinx_srl to use 'slice' features of pmgen for word level
2019-08-23 12:22:06 -07:00
Eddie Hung
f4fd41d5d2
Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
2019-08-23 11:35:06 -07:00
Eddie Hung
78b7d8f531
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-23 11:32:44 -07:00
Eddie Hung
d672b1ddec
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-23 11:26:55 -07:00
Eddie Hung
619f2414e5
clkbufmap to only check clkbuf_inhibit if no selection given
2019-08-23 11:14:42 -07:00
Eddie Hung
4d89c3f468
Review comment from @cliffordwolf
2019-08-23 10:03:41 -07:00
Eddie Hung
6872805a3e
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-23 10:00:50 -07:00
Clifford Wolf
55bf8f69e0
Fix port hanlding in pmgen
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-23 16:26:54 +02:00
Clifford Wolf
adb81ba386
Add pmgen slices and choices
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-23 16:15:50 +02:00
Eddie Hung
51ffb093b5
In sat: 'x' in init attr should not override constant
2019-08-22 16:43:08 -07:00
Eddie Hung
2b37a093e9
In sat: 'x' in init attr should not override constant
2019-08-22 16:42:19 -07:00
Eddie Hung
53fed4f7e9
Actually, there might not be any harm in updating sigmap...
2019-08-22 16:16:56 -07:00
Eddie Hung
cfafd360d5
Add comment as per @cliffordwolf
2019-08-22 16:16:56 -07:00
Eddie Hung
8691596d19
Revert "Try way that doesn't involve creating a new wire"
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This reverts commit 2f427acc9e
.
2019-08-22 16:16:34 -07:00
Eddie Hung
5ff75b1cdc
Try way that doesn't involve creating a new wire
2019-08-22 16:16:34 -07:00
Eddie Hung
e1fff34dde
If d_bit already in sigbit_chain_next, create extra wire
2019-08-22 16:16:34 -07:00
Eddie Hung
c50d68653d
Spelling
2019-08-22 16:06:36 -07:00
Eddie Hung
6e8fda8bf0
Add doc
2019-08-22 11:52:24 -07:00
Eddie Hung
cabadb85e2
Add copyright
2019-08-22 11:25:19 -07:00
Eddie Hung
36d94caec1
Remove `shregmap -tech xilinx` additions
2019-08-22 11:22:09 -07:00
Eddie Hung
9f3ed1726e
pmgen to also iterate over all module ports
2019-08-22 11:15:16 -07:00
Eddie Hung
74bd190d3b
Remove output_bits
2019-08-22 11:14:59 -07:00
Eddie Hung
231ddbf95c
Forgot to set ud_variable.minlen
2019-08-22 11:02:17 -07:00
Eddie Hung
61639d5387
Do not run xilinx_srl_pm in fixed loop
2019-08-22 10:51:04 -07:00
Eddie Hung
7188972645
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-22 10:32:54 -07:00
Eddie Hung
d0b2973413
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-22 10:32:06 -07:00
Eddie Hung
b800059fc1
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
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opt_expr to trim A port of $shiftx/$shift
2019-08-22 10:31:27 -07:00
Eddie Hung
9245f0d3f5
Copy-paste typo
2019-08-22 08:43:44 -07:00
Eddie Hung
6f971470f8
Respect opt_expr -keepdc as per @cliffordwolf
2019-08-22 08:37:27 -07:00
Eddie Hung
379f33af54
Handle $shift and Y_WIDTH > 1 as per @cliffordwolf
2019-08-22 08:22:23 -07:00
Eddie Hung
9e31f01b34
Add cover()
2019-08-22 08:06:24 -07:00
Eddie Hung
d0ffe7544c
Canonical form
2019-08-22 08:05:01 -07:00
Eddie Hung
d3a212ff91
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
2019-08-21 21:53:55 -07:00
Eddie Hung
7d02d17b16
Reuse var
2019-08-21 19:18:40 -07:00
Eddie Hung
5c8344363f
Revert "Trim shiftx_width when upper bits are 1'bx"
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This reverts commit 7e7965ca7b
.
2019-08-21 19:18:27 -07:00
Eddie Hung
c7859531c2
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
2019-08-21 19:18:05 -07:00
Eddie Hung
7e7965ca7b
Trim shiftx_width when upper bits are 1'bx
2019-08-21 18:43:17 -07:00
Eddie Hung
ed7be3e6b6
Add comment
2019-08-21 17:36:38 -07:00
Eddie Hung
15188033da
Add variable length support to xilinx_srl
2019-08-21 17:34:40 -07:00
Eddie Hung
6d76ae4c65
Rename pattern to fixed
2019-08-21 15:46:58 -07:00
Eddie Hung
b0a3b430bf
attribute -> attr
2019-08-21 15:44:07 -07:00
Eddie Hung
61b4d7ae13
Use Cell::has_keep_attribute()
2019-08-21 15:41:46 -07:00
Eddie Hung
6fa9e03e4c
xilinx_srl to support FDRE and FDRE_1
2019-08-21 15:35:29 -07:00
Eddie Hung
3c8e8521a6
Fix polarity of EN_POL
2019-08-21 14:42:11 -07:00
Eddie Hung
a980f0d4be
Add CLKPOL == 0
2019-08-21 14:35:40 -07:00
Eddie Hung
1c7d721558
Reject if not minlen from inside pattern matcher
2019-08-21 14:26:24 -07:00
Eddie Hung
cab2bd083e
Get wire via SigBit
2019-08-21 13:47:47 -07:00
Eddie Hung
52fea5b658
Respect \keep on cells or wires
2019-08-21 13:42:03 -07:00
Eddie Hung
5ce0c31d0e
Add init support
2019-08-21 13:05:10 -07:00
Eddie Hung
df53fe12e7
Fix spacing
2019-08-21 12:54:11 -07:00
Eddie Hung
0250712486
Initial progress on xilinx_srl
2019-08-21 12:50:49 -07:00
Eddie Hung
8f69be9cc7
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-21 11:39:14 -07:00
Miodrag Milanovic
948b6f91a1
Fix test_pmgen deps
2019-08-21 17:00:24 +02:00
Clifford Wolf
7d8db1c053
Merge pull request #1314 from YosysHQ/eddie/fix_techmap
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techmap -max_iter to apply to each module individually
2019-08-21 09:12:56 +02:00
Eddie Hung
4cc74346f1
Fix compile error
2019-08-20 20:27:05 -07:00
Eddie Hung
9b9d759451
Fix copy-paste typo
2019-08-20 20:18:51 -07:00
Eddie Hung
b7a48e3e0f
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-20 20:18:17 -07:00
Eddie Hung
affe9c9c1a
Merge branch 'eddie/fix_techmap' into xaig_arrival
2019-08-20 20:06:47 -07:00
Eddie Hung
fe61dcce8b
Grammar
2019-08-20 20:05:51 -07:00
Eddie Hung
193eae0c84
techmap -max_iter to apply to each module individually
2019-08-20 19:50:20 -07:00
Eddie Hung
57493e328a
techmap -max_iter to apply to each module individually
2019-08-20 19:48:16 -07:00
Eddie Hung
f1a206ba03
Revert "Remove sequential extension"
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This reverts commit 091bf4a18b
.
2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
fad15d276d
retime_mode -> dff_mode
2019-08-20 18:08:58 -07:00
Eddie Hung
505d062daf
Fix use of {CLK,EN}_POLARITY, also add a FIXME
2019-08-20 13:33:31 -07:00
Eddie Hung
c4d4c6db3f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 12:00:12 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
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Refactor abc9 to use port attributes, not module attributes
2019-08-20 11:59:31 -07:00
Clifford Wolf
d0117d7d12
Merge branch 'master' into clifford/pmgen
2019-08-20 11:39:23 +02:00
whitequark
749ff864aa
Merge pull request #1309 from whitequark/proc_clean-fix-1268
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proc_clean: fix order of switch insertion
2019-08-20 00:45:41 +00:00
Eddie Hung
1f03154a0c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 15:19:32 -07:00
Eddie Hung
e29df7d5fa
Remove debug
2019-08-19 12:44:43 -07:00
Eddie Hung
91687d3fea
Add (* abc_arrival *) attribute
2019-08-19 12:33:24 -07:00
Eddie Hung
ba2261e21a
Move from cell attr to module attr
2019-08-19 11:18:33 -07:00
Eddie Hung
7e010834eb
Fix typo
2019-08-19 10:41:18 -07:00
Eddie Hung
f42ba811b6
ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc
2019-08-19 10:11:47 -07:00
Eddie Hung
2f4e0a5388
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 10:07:27 -07:00
Eddie Hung
d81a090d89
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
2019-08-19 09:56:17 -07:00
Eddie Hung
e301440a0b
Use attributes instead of params
2019-08-19 09:51:49 -07:00
whitequark
4a942ba7b9
proc_clean: fix order of switch insertion.
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Fixes #1268 .
2019-08-19 16:44:23 +00:00
Eddie Hung
9bfe924e17
Set abc_flop and use it in toposort
2019-08-19 09:40:01 -07:00
Clifford Wolf
1e3dd0a2da
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
2019-08-19 13:04:06 +02:00
Miodrag Milanovic
dbe3cb9708
Ignore all generated headers for pmgen pass
2019-08-18 10:49:17 +02:00
whitequark
101235400c
Merge branch 'master' into eddie/pr1266_again
2019-08-18 08:04:10 +00:00
Clifford Wolf
2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255
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Fix various NDEBUG compiler warnings
2019-08-17 15:07:16 +02:00
Clifford Wolf
ae5d8dc939
Merge pull request #1303 from YosysHQ/bogdanvuk/opt_share
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Implement opt_share from @bogdanvuk
2019-08-17 15:03:46 +02:00
Clifford Wolf
8915f496d9
Merge pull request #1300 from YosysHQ/eddie/cleanup2
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Use ID::{A,B,Y,keep,blackbox,whitebox} instead of ID()
2019-08-17 15:01:31 +02:00
Clifford Wolf
f3405fb048
Refactor pmgen rollback mechanism
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 13:54:18 +02:00
Clifford Wolf
318ae0351c
Improvements in "test_pmgen -generate"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 13:53:55 +02:00
Clifford Wolf
f95853c822
Add pmgen "fallthrough" statement
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-17 11:29:37 +02:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
5abe133323
Use ID()
2019-08-16 16:38:49 -07:00
Eddie Hung
4fe307f1bc
Compute abc_scc_break and move CI/CO outside of each abc9
2019-08-16 15:41:17 -07:00
Eddie Hung
3d3779b037
Use ID() macro
2019-08-16 14:01:55 -07:00
Eddie Hung
fab067cece
Add 'opt_share' to 'opt -full'
2019-08-16 13:47:37 -07:00
Eddie Hung
51d28645da
Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_share
2019-08-16 13:40:29 -07:00
Eddie Hung
6b51c154c6
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-16 13:38:47 -07:00
Eddie Hung
cd5a372cd1
Add help() call
2019-08-16 13:00:12 -07:00
Eddie Hung
29e14e674e
Remove `using namespace RTLIL;`
2019-08-16 19:36:45 +00:00
Clifford Wolf
64bd414e54
Minor bugfix in "test_pmgen -generate"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 14:35:13 +02:00
Clifford Wolf
958be89c47
Merge pull request #1302 from mmicko/dfflibmap_regression
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DFFLIBMAP pass regression fix
2019-08-16 14:26:58 +02:00
Clifford Wolf
20910fd7c8
Add pmgen finish statement, return number of matches
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 14:16:35 +02:00
Clifford Wolf
f45dad8220
Redesign pmgen backtracking for recursive matching
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 13:47:50 +02:00
Clifford Wolf
c710df181c
Add pmgen "generate" feature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 13:26:36 +02:00
Miodrag Milanovic
72eacdb9f8
Regression in abc9
2019-08-16 13:21:11 +02:00
Miodrag Milanovic
bb79e050a5
Just needed IDs to be IdString
2019-08-16 11:50:34 +02:00
Clifford Wolf
4a57b7e1ab
Refactor demo_reduce into test_pmgen
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 11:47:51 +02:00
Clifford Wolf
bb37a20e8d
Add missing NMUX to "abc -g" handling
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-16 10:36:11 +02:00
Eddie Hung
eae5a6b12c
Use ID::keep more liberally too
2019-08-15 14:51:12 -07:00
Eddie Hung
52355f5185
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
Clifford Wolf
016036f247
Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-15 23:02:37 +02:00
Clifford Wolf
969ab9027a
Update pmgen documentation
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-15 22:48:13 +02:00
Clifford Wolf
eb80d3d43f
Change pmgen default rule to reject, switch peepopt behavior to accept
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-15 22:47:59 +02:00
Clifford Wolf
49301b733e
Merge branch 'master' into clifford/fix1255
2019-08-15 22:44:38 +02:00
Eddie Hung
c320abc3f4
xilinx_dsp to be sensitive to keep attribute
2019-08-15 12:34:11 -07:00
Eddie Hung
96ee7b9cf7
Simplify
2019-08-15 12:30:46 -07:00
Eddie Hung
7f10019610
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-15 12:19:51 -07:00
Eddie Hung
27d5df9467
ffH -> ffFJKG
2019-08-15 12:19:34 -07:00
Eddie Hung
6cd8cace0c
Fix
2019-08-15 11:25:42 -07:00
Eddie Hung
02dead2e60
ID(\\.*) -> ID(.*)
2019-08-15 10:25:54 -07:00
Eddie Hung
467c34eff0
Convert a few more to ID
2019-08-15 10:24:35 -07:00
Eddie Hung
78ba8b8574
Transform all "\\*" identifiers into ID()
2019-08-15 10:19:29 -07:00
Eddie Hung
9f98241010
Transform "$.*" to ID("$.*") in passes/techmap
2019-08-15 10:05:08 -07:00
Clifford Wolf
03f98d9176
Add demo_reduce pass to demonstrace recursive pattern matching
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-15 18:36:39 +02:00
Clifford Wolf
73bf453929
Improvements in pmgen for recursive patterns
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-15 18:35:56 +02:00
Eddie Hung
4cfefae21e
More use of IdString::in()
2019-08-15 09:23:57 -07:00
Eddie Hung
91f6cdfef6
Merge remote-tracking branch 'origin/master' into eddie/fix_1284_again
2019-08-15 06:48:40 -07:00
Clifford Wolf
85b0b2c589
Merge branch 'master' into clifford/ids
2019-08-15 10:22:59 +02:00
Eddie Hung
1551e14d2d
AND with an inverted input, causes X{,N}OR output to be inverted too
2019-08-14 16:26:24 -07:00
Eddie Hung
1e47e81869
Revert "Only sort leaves on non-ANDNOT/ORNOT cells"
...
This reverts commit 5ec5f6dec7
.
2019-08-14 15:23:25 -07:00
Eddie Hung
5ec5f6dec7
Only sort leaves on non-ANDNOT/ORNOT cells
2019-08-14 11:25:56 -07:00
Eddie Hung
0e128510c0
Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves"
2019-08-14 10:40:53 -07:00
Eddie Hung
aad97168b0
Fixes for reverting SigSpec helper functions
2019-08-14 10:22:33 -07:00
Eddie Hung
2f04beeeb5
Perform C -> PCIN optimisation after pattern matcher
2019-08-13 17:11:35 -07:00
Eddie Hung
1b0e68db94
Revert changes to RTLIL::SigSpec methods
2019-08-13 17:09:28 -07:00
Marcin Kościelnicki
3c75a72feb
move attributes to wires
2019-08-13 19:36:59 +00:00
Eddie Hung
0597a3ea23
Rename to XilinxDspPass
2019-08-13 10:23:07 -07:00
Clifford Wolf
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
Marcin Kościelnicki
c6d5b97b98
review fixes
2019-08-13 00:35:54 +00:00
Marcin Kościelnicki
f4c62f33ac
Add clock buffer insertion pass, improve iopadmap.
...
A few new attributes are defined for use in cell libraries:
- iopad_external_pin: marks PAD cell's external-facing pin. Pad
insertion will be skipped for ports that are already connected
to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
Clock buffer insertion will be skipped for nets that are already
driven by such a pin.
All three are module attributes that should be set to a comma-separeted
list of pin names.
Clock buffer insertion itself works as follows:
1. All cell ports, starting from bottom up, can be marked as clock sinks
(requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
also connected to a clock sink port in a contained cell, a clock
buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
connected to clock sinks, optionally with a special kind of input
PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
attribute is set on it.
2019-08-13 00:16:38 +02:00
Eddie Hung
12c692f6ed
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
...
This reverts commit c851dc1310
, reversing
changes made to f54bf1631f
.
2019-08-12 12:06:45 -07:00
Eddie Hung
f890cfb63b
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-12 11:32:10 -07:00
Eddie Hung
e4a0971581
Since $_ANDNOT_ is not symmetric, do not sort leaves
2019-08-12 11:17:15 -07:00
Eddie Hung
88d5185596
Merge remote-tracking branch 'origin/master' into eddie/fix_1262
2019-08-11 21:13:40 -07:00
Clifford Wolf
6995914f3f
Use ID() macro in all of passes/opt/
...
This was obtained by running the following SED command in passes/opt/
and then using "meld foo.cc foo.cc.orig" to manually fix all resulting
compiler errors.
sed -i.orig -r 's/"\\\\([a-zA-Z0-9_]+)"/ID(\1)/g; s/"(\$[a-zA-Z0-9_]+)"/ID(\1)/g;' *.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 11:39:46 +02:00
Eddie Hung
282cc77604
Wrong way around
2019-08-10 11:55:00 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"
2019-08-10 17:14:48 +01:00
Eddie Hung
02b0d328ad
cover_list -> cover as per @cliffordwolf
2019-08-10 08:26:41 -07:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
...
Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
dad9514d86
Merge pull request #1276 from YosysHQ/clifford/fix1273
...
Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib
2019-08-10 09:38:22 +02:00
Eddie Hung
ab1d63a565
Check nusers of DSP output, not whole flop
2019-08-09 17:35:13 -07:00
Eddie Hung
3dd3ab98c2
Improve ice40_dsp for non-fully-32-bit adders
2019-08-09 17:23:12 -07:00
Eddie Hung
dfc878deb4
Another filter -> if
2019-08-09 16:23:32 -07:00
Eddie Hung
e83f231927
Cleanup
2019-08-09 15:47:40 -07:00
Eddie Hung
0b5b56c1ec
Pack partial-product adder DSP48E1 packing
2019-08-09 15:19:33 -07:00
Eddie Hung
a002eba14a
Fix check
2019-08-09 14:27:08 -07:00
Eddie Hung
82cbfada1b
Revert "Fix typo"
...
This reverts commit e3c39cc450
.
2019-08-09 14:14:28 -07:00
Eddie Hung
849e0eeab4
Grammar
2019-08-09 12:43:21 -07:00
Eddie Hung
31f6d74552
Separate $alu handling
2019-08-09 12:13:32 -07:00
Eddie Hung
9f1b82f594
opt_expr -fine to trim LSBs of $alu too
2019-08-09 10:32:12 -07:00
Clifford Wolf
6d0be8d206
Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes #1273
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-09 19:17:59 +02:00
whitequark
39f4c1096a
Merge pull request #1267 from whitequark/proc_prune-fix-1243
...
proc_prune: fix handling of exactly identical assigns
2019-08-09 17:10:46 +00:00
Eddie Hung
747690a6df
Remove muxY and ffY for now
2019-08-08 16:33:37 -07:00
Eddie Hung
2c0be7aa5d
Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
2019-08-08 12:56:05 -07:00
Eddie Hung
07e50b9c25
Only pack registers if {A,B,P}REG = 0, do not pack $dffe
2019-08-08 10:51:19 -07:00
Eddie Hung
911129e3ef
Disable $dffe
2019-08-08 10:44:49 -07:00
Eddie Hung
ac2fc3a144
Merge pull request #1264 from YosysHQ/eddie/fix_1254
...
opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
2019-08-08 07:58:33 -07:00
whitequark
0b09a347dc
proc_prune: fix handling of exactly identical assigns.
...
Before this commit, in a process like:
process $proc$bug.v:8$3
assign $foo \bar
switch \sel
case 1'1
assign $foo 1'1
assign $foo 1'1
case
assign $foo 1'0
end
end
both of the "assign $foo 1'1" would incorrectly be removed.
Fixes #1243 .
2019-08-08 05:32:35 +00:00
Eddie Hung
675c1d4218
Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER
2019-08-07 16:29:38 -07:00
Eddie Hung
fb568ddb4e
Fix compile error
2019-08-07 14:31:55 -07:00
Eddie Hung
d90b8b081a
Do not SigSpec::extract() beyond bounds
2019-08-07 13:58:26 -07:00
Eddie Hung
e3d898dccb
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-07 13:44:08 -07:00
Eddie Hung
f69410daaf
opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
2019-08-07 13:15:02 -07:00
Eddie Hung
cdf9c80134
Do not pack registers if (* keep *)
2019-08-07 12:57:10 -07:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Eddie Hung
0c78c62d6c
Remove std:: namespace
2019-08-07 11:11:14 -07:00
Eddie Hung
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
Eddie Hung
58e512ab70
Add comment
2019-08-07 09:54:27 -07:00
Eddie Hung
f20acbc813
Revert "Add TODO"
...
This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
2019-08-07 09:54:27 -07:00
Eddie Hung
789585a744
Add TODO
2019-08-07 09:54:27 -07:00
Eddie Hung
8a8c1d7857
Compute box_lookup just once
2019-08-07 09:54:27 -07:00
Clifford Wolf
e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
...
wreduce/opt_expr: improve width reduction for $add and $sub cells
2019-08-07 14:27:35 +02:00
Clifford Wolf
338f6765eb
Tweak default gate costs, cleanup "stat -tech cmos"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 10:25:51 +02:00
Bogdan Vukobratovic
067b44938c
Fix wrong results when opt_share called before opt_clean
2019-08-07 09:30:58 +02:00
Eddie Hung
ee7c970367
IdString::str().substr() -> IdString::substr()
2019-08-06 19:08:33 -07:00
Eddie Hung
234fcf1724
Fix typos
2019-08-06 19:07:45 -07:00
Eddie Hung
c11ad24fd7
Use std::stoi instead of atoi(<str>.c_str())
2019-08-06 16:45:48 -07:00
Eddie Hung
e38f40af5b
Use IdString::begins_with()
2019-08-06 16:42:25 -07:00
Eddie Hung
046e1a5214
Use State::S{0,1}
2019-08-06 16:22:47 -07:00
Eddie Hung
3486235338
Make liberal use of IdString.in()
2019-08-06 16:18:18 -07:00
Clifford Wolf
100c377451
Redesign of cell cost API
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 01:12:14 +02:00
Eddie Hung
43081337fa
Cleanup opt_expr.cc
2019-08-06 16:04:21 -07:00
Eddie Hung
bfc7164af7
Move LSB-trimming functionality from wreduce to opt_expr
2019-08-06 15:25:50 -07:00
Eddie Hung
26cb3e7afc
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add
2019-08-06 14:50:00 -07:00
Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Bogdan Vukobratovic
6a796accc0
Support various binary operators in opt_share
2019-08-04 19:06:38 +02:00
Bogdan Vukobratovic
280c4e7794
Fix spacing in opt_share tests, change wording in opt_share help
2019-08-03 12:28:46 +02:00
whitequark
44a9dcbbbf
Merge pull request #1242 from jfng/fix-proc_prune-partial
...
proc_prune: Promote partially redundant assignments.
2019-08-03 07:08:41 +00:00
Clifford Wolf
0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix
...
Visual Studio build fix
2019-08-02 17:07:39 +02:00
Eddie Hung
c39b1a6fcf
Add comment about supporting $dffe in ice40_dsp
2019-08-01 15:13:18 -07:00
Eddie Hung
ed7540a46f
Pack P register properly
2019-08-01 15:10:43 -07:00
Eddie Hung
e19d33b003
Cope with sign extension in mul2dsp
2019-08-01 12:44:56 -07:00
Eddie Hung
ed303b07b7
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-08-01 12:02:16 -07:00
Eddie Hung
c54a39069d
CO is sign extension only if signed multiplier
2019-08-01 10:00:49 -07:00
Eddie Hung
e3c39cc450
Fix typo
2019-08-01 10:00:01 -07:00
Miodrag Milanovic
28b7053a01
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
Jean-François Nguyen
320bf2fde5
proc_prune: Promote partially redundant assignments.
2019-08-01 13:09:55 +02:00
Eddie Hung
e4a638c292
Restore old CO behaviour
2019-07-31 15:45:15 -07:00
Miodrag Milanovic
35d28de478
Visual Studio build fix
2019-07-31 09:10:24 +02:00
Bogdan Vukobratovic
c075486c59
Reimplement opt_share to work on $alu and $pmux
2019-07-28 16:03:54 +02:00
Eddie Hung
07e38d8d5c
Update test_autotb doc to reflect default value of zero
2019-07-26 12:37:30 -07:00
Eddie Hung
8cecad5059
Add doc for "test_autotb -seed" option
2019-07-26 12:26:54 -07:00
Eddie Hung
4c25d1a76f
Pop the CO bit from O
2019-07-26 10:27:30 -07:00
Eddie Hung
c1a05f4557
Allow adders/accumulators with 33 bits using CO output
2019-07-26 10:15:36 -07:00
Bogdan Vukobratovic
07c4a7d438
Implement opt_share
...
This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
2019-07-26 11:36:48 +02:00
Eddie Hung
79fd6edc5a
Eliminate warnings by sizing O correctly
2019-07-23 15:13:30 -07:00
Eddie Hung
a37574ccbf
Fix muxAB logic
2019-07-23 14:52:14 -07:00
Eddie Hung
0dd2a125f6
Remove debug print
2019-07-23 14:21:45 -07:00
Eddie Hung
dc0c853abe
Simplify and fix for MACs
2019-07-23 14:20:34 -07:00
Eddie Hung
4f11ff8ebd
Fix typo
2019-07-23 13:58:56 -07:00
Eddie Hung
33c984a044
Fix spacing
2019-07-22 16:37:13 -07:00
Eddie Hung
068617f094
Pack hi and lo registers separately
2019-07-22 16:12:57 -07:00
Eddie Hung
4d71ab384d
Rename according to vendor doc TN1295
2019-07-22 15:08:26 -07:00
Eddie Hung
304cefbbe2
Pack Y register
2019-07-22 15:05:16 -07:00
Eddie Hung
5a14b6e1f6
Pack adders not just accumulators
2019-07-22 13:01:49 -07:00
Clifford Wolf
c6d8692c97
Add "stat -tech cmos"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-20 15:06:28 +02:00
Eddie Hung
e0720a8018
Restore old ffY behaviour
2019-07-19 22:47:08 -07:00
Eddie Hung
f9d08a5e5e
Cleanup
2019-07-19 20:25:28 -07:00
Eddie Hung
09beeee38a
Try and fix again
2019-07-19 14:40:57 -07:00
Eddie Hung
e87916b7eb
Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp
2019-07-19 14:03:34 -07:00
Eddie Hung
cb0fd05215
Do not access beyond bounds
2019-07-19 13:58:50 -07:00
Eddie Hung
3a87dc3524
Wrap A and B in sigmap
2019-07-19 13:23:07 -07:00
Eddie Hung
31b0002e8c
Remove "top" from message
2019-07-19 13:20:45 -07:00
Eddie Hung
8791e0caac
Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dsp
2019-07-19 13:18:20 -07:00
Eddie Hung
bcd8027182
Also optimise MSB of $sub
2019-07-19 13:11:48 -07:00
Eddie Hung
fc0e36d1c0
wreduce for $sub
2019-07-19 12:50:21 -07:00
Eddie Hung
9ad11ea2cc
Fine tune ice40_dsp.pmg, add support for packing subsets of registers
2019-07-19 10:57:32 -07:00
Eddie Hung
8f0e796be1
Add support for ice40 signed multipliers
2019-07-19 10:38:13 -07:00
Eddie Hung
42e40dbd0a
Merge remote-tracking branch 'origin/master' into ice40dsp
2019-07-18 15:45:25 -07:00
Eddie Hung
09411dd996
ice40_dsp to accept $__MUL16X16 too
2019-07-18 15:38:28 -07:00
Eddie Hung
802470746c
Check if RHS is empty first
2019-07-18 15:22:00 -07:00
Eddie Hung
90ac147eb2
Do not autoremove ffP aor muxP
2019-07-18 15:02:41 -07:00
Eddie Hung
08fe63c61e
Improve pattern matcher to match subsets of $dffe? cells
2019-07-18 14:08:18 -07:00
Eddie Hung
79d63479ea
Improve A/B reg packing
2019-07-18 13:30:35 -07:00
Eddie Hung
e075f0dda0
Do not autoremove A/B registers since they might have other consumers
2019-07-18 13:22:22 -07:00
Eddie Hung
0727b2c902
Fix xilinx_dsp index cast
2019-07-18 13:18:04 -07:00
Eddie Hung
c76607b9bc
Wrong wildcard symbol
2019-07-18 08:14:58 -07:00
Eddie Hung
91629ee4b3
Pattern matcher to check pool of bits, not exactly
2019-07-17 12:45:25 -07:00
Eddie Hung
3f677fb0db
Signed extension
2019-07-16 15:54:07 -07:00
Eddie Hung
9616dbd125
Add support {A,B,P}REG packing
2019-07-16 14:06:32 -07:00
Eddie Hung
5939b5d636
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
...
abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
2019-07-16 08:53:47 -07:00
Eddie Hung
ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix
...
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
2019-07-16 08:52:14 -07:00
Miodrag Milanovic
2b469e82a7
Fix check logic in extract_fa
2019-07-16 10:35:18 +02:00
Eddie Hung
5f00d335d4
Oops forgot these files
2019-07-15 15:03:15 -07:00
Eddie Hung
dd59375a66
Add xilinx_dsp for register packing
2019-07-15 14:46:31 -07:00
Clifford Wolf
2a7198db51
Merge pull request #1189 from YosysHQ/eddie/fix1151
...
Error out if enable > dbits in memory_bram file
2019-07-15 20:06:35 +02:00
Clifford Wolf
2c5c53e4c1
Merge pull request #1190 from YosysHQ/eddie/fix_1099
...
extract_fa to return nothing more gracefully
2019-07-15 20:05:56 +02:00
whitequark
2de7e92bb8
opt_lut: make less chatty.
2019-07-13 16:49:56 +00:00
Eddie Hung
9b91d815b5
If ConstEval fails do not log_abort() but return gracefully
2019-07-13 04:13:57 -07:00
Eddie Hung
ab3917d079
Error out if enable > dbits
2019-07-13 03:39:23 -07:00
Eddie Hung
fb062c3426
Add comment
2019-07-13 00:52:21 -07:00
Eddie Hung
e9bdc86c0e
duplicate -> clone
2019-07-12 19:33:02 -07:00
Eddie Hung
be0cb7f4b8
More cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
7d583f9e57
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
83f23a24a8
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
1adbfb5533
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
39a7c7c54c
More cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
91c07be196
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
399e1ec870
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
58dbb28fd3
Cleanup
2019-07-12 19:30:18 -07:00
Eddie Hung
7dc15bdd2d
Do not double count cells in abc
2019-07-12 08:22:26 -07:00
Eddie Hung
237d8651a5
Error out if abc9 not called with -lut or -luts
2019-07-11 09:58:00 -07:00
Eddie Hung
0c3ed73dad
Count $_NOT_ cells turned into $luts
2019-07-11 09:55:14 -07:00
Eddie Hung
33862d0445
WIP for fixing partitioning, temporarily do not partition
2019-07-11 09:22:52 -07:00
Eddie Hung
c0abd18799
Enable &mfs for abc9, even if it only currently works for ice40
2019-07-11 08:49:06 -07:00
Clifford Wolf
fd3d5cefad
Merge pull request #1179 from whitequark/attrmap-proc
...
attrmap: also consider process, switch and case attributes
2019-07-11 07:23:28 +02:00
Eddie Hung
9f608d6be3
write_verilog with *.v extension
2019-07-10 20:25:59 -07:00
Eddie Hung
71acd3ddcf
Remove -retime from abc9, revert to abc behav with separate clock/en domains
2019-07-10 18:57:44 -07:00
Eddie Hung
052060f109
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-10 16:05:41 -07:00
whitequark
ea447220da
attrmap: also consider process, switch and case attributes.
2019-07-10 12:30:53 +00:00
Clifford Wolf
c66b4b9131
Merge pull request #1177 from YosysHQ/clifford/async
...
Fix clk2fflogic adff reset semantic to negative hold time on reset
2019-07-10 08:48:20 +02:00
Clifford Wolf
cae26bf330
Merge pull request #1174 from YosysHQ/eddie/fix1173
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Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
2019-07-09 22:59:51 +02:00
Clifford Wolf
9546ccdbd3
Fix tests/various/async FFL test
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 22:44:39 +02:00
Eddie Hung
c2db70f41e
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
2019-07-09 12:14:00 -07:00
Eddie Hung
713337255e
Revert "Add "synth -keepdc" option"
2019-07-09 10:14:23 -07:00
Clifford Wolf
e95ce1f7af
Merge pull request #1168 from whitequark/bugpoint-processes
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Add support for processes in bugpoint
2019-07-09 16:59:43 +02:00
Clifford Wolf
a0787c12f0
Merge pull request #1169 from whitequark/more-proc-cleanups
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A new proc_prune pass
2019-07-09 16:59:18 +02:00
Clifford Wolf
38e942507e
Merge pull request #1163 from whitequark/more-case-attrs
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More support for case rule attributes
2019-07-09 16:57:16 +02:00
whitequark
44bcb7a187
proc_prune: promote assigns to module connections when legal.
...
This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)
2019-07-09 09:30:58 +00:00
whitequark
5fe0ffe30f
proc_prune: new pass.
...
The proc_prune pass is similar in nature to proc_rmdead pass: while
proc_rmdead removes branches that never become active because another
branch preempts it, proc_prune removes assignments that never become
active because another assignment preempts them.
Genrtlil contains logic similar to the proc_prune pass, but their
purpose is different: genrtlil has to prune assignments to adapt
the semantics of blocking assignments in HDLs (latest assignment
wins) to semantics of assignments in RTLIL processes (assignment in
the most specific case wins). On the other hand proc_prune is
a general purpose RTLIL simplification that benefits all frontends,
even those not using the Yosys AST library.
The proc_prune pass is added to the proc script after proc_rmdead,
since it gives better results with fewer branches.
2019-07-09 09:30:58 +00:00
whitequark
f2fb958d44
bugpoint: add -assigns and -updates options.
2019-07-09 09:27:43 +00:00
whitequark
f7a14a5678
proc_clean: add -quiet option.
...
This is useful for other passes that call it often, like bugpoint.
2019-07-09 09:27:43 +00:00
Eddie Hung
37b58f4324
Clarify 'wreduce -keepdc' doc
2019-07-08 19:15:07 -07:00
Eddie Hung
b5072256f2
Update muxcover doc as per @ZirconiumX
2019-07-08 12:50:59 -07:00
Eddie Hung
3681162c8d
atoi -> stoi
2019-07-08 11:00:06 -07:00
Eddie Hung
a34c5612e7
Add muxcover -mux2=cost option
2019-07-08 10:59:12 -07:00
whitequark
48655dfb8b
proc_mux: consider \src attribute on CaseRule.
2019-07-08 13:18:18 +00:00
Eddie Hung
35fd9b0473
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-02 12:35:45 -07:00
David Shah
d45936fe5f
memory_dff: Fix checking of feedback mux input when more than one mux
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-02 13:35:50 +01:00
Eddie Hung
ef757002db
Also remove $__ABC_FF_
2019-07-01 10:55:24 -07:00
Eddie Hung
699d8e3939
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-07-01 10:44:42 -07:00
Gabriel L. Somlo
8cb3655ecd
Make abc9 pass aware of optional ABCEXTERNAL override
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-28 14:56:16 -04:00
Eddie Hung
4a2a93aa06
Fix spacing
2019-06-28 11:10:36 -07:00
Eddie Hung
da5f830395
Merge pull request #1098 from YosysHQ/xaig
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"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
2019-06-28 10:59:03 -07:00
Clifford Wolf
1c7ce251f3
Merge pull request #1046 from bogdanvuk/master
...
Optimizing DFFs whose initial value prevents their value from changing
2019-06-28 08:30:18 +02:00
Eddie Hung
a625854ac5
Do not use Module::remove() iterator version
2019-06-27 15:29:20 -07:00
Eddie Hung
137c91d9a9
Remove &retime when abc9 -fast
2019-06-27 15:17:39 -07:00
Eddie Hung
6bf73e3546
Cleanup abc9.cc
2019-06-27 15:15:56 -07:00
Bogdan Vukobratovic
3225bfb984
Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too
2019-06-27 22:06:23 +02:00
Bogdan Vukobratovic
35fa7b3057
Fix memory leak when one of multiple DFF cells is removed in opt_rmdff
...
When there are multiple DFFs and one of them is removed, its reference lingers
inside bit2driver dict. While invoking handle_dff() function for other DFFs,
this broken reference is used isnside sat_import_cell() function.
2019-06-27 22:02:12 +02:00
Eddie Hung
440f173aef
Merge remote-tracking branch 'origin/master' into xaig
2019-06-27 11:54:34 -07:00
Eddie Hung
6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135
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Add "pmux2shiftx -norange"
2019-06-27 11:48:48 -07:00
Eddie Hung
6c256b8cda
Merge origin/master
2019-06-27 11:20:15 -07:00
Bogdan Vukobratovic
0f32cb4e0a
Merge remote-tracking branch 'upstream/master'
2019-06-27 12:11:47 +02:00
Clifford Wolf
7c14678ec0
Add "pmux2shiftx -norange", fixes #1135
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-27 10:59:12 +02:00
Clifford Wolf
69d810e4a8
Fix handling of partial covers in muxcover, fixes #1132
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-27 09:42:58 +02:00
Eddie Hung
c226af3f56
Fix spacing
2019-06-26 20:03:34 -07:00
Eddie Hung
26efd6f0a9
Support more than one port in the abc_scc_break attr
2019-06-26 19:57:54 -07:00
Clifford Wolf
0b7d648c6a
Improve opt_clean handling of unused public wires
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-26 17:54:17 +02:00
Clifford Wolf
8e9ef891fe
Do not clean up buffer cells with "keep" attribute, closes #1128
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-26 11:01:03 +02:00
Eddie Hung
5db96b8aec
Missing muxpack.o in Makefile
2019-06-25 10:38:42 -07:00
Eddie Hung
6f36ec8ecf
Merge remote-tracking branch 'origin/master' into xaig
2019-06-25 09:33:11 -07:00
Clifford Wolf
add2d415fc
Merge pull request #1130 from YosysHQ/eddie/fix710
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memory_dff: walk through more than one mux for computing read enable
2019-06-25 17:34:44 +02:00
Eddie Hung
42720ef6fe
Fix spacing
2019-06-25 08:33:17 -07:00
Eddie Hung
c4e4902098
Move only one consumer check outside of while loop
2019-06-25 08:29:55 -07:00
Eddie Hung
d2fed0a7f1
nullptr check
2019-06-25 06:06:32 -07:00
Eddie Hung
a19226c174
Fix for abc_scc_break is bus
2019-06-24 22:16:56 -07:00
Eddie Hung
5605002d8a
More meaningful error message
2019-06-24 22:12:55 -07:00
Eddie Hung
babadf5938
Do not use log_id as it strips \\, also fix scc for |wire| > 1
2019-06-24 22:04:22 -07:00
Eddie Hung
49a762ba46
Fix abc9's scc breaker, also break on abc_scc_break attr
2019-06-24 21:53:18 -07:00
Eddie Hung
b7deaceadd
Walk through as many muxes as exist for rd_en
2019-06-24 18:33:06 -07:00
Eddie Hung
4ddc0354c1
Merge remote-tracking branch 'origin/master' into eddie/muxpack
2019-06-22 14:40:55 -07:00
Eddie Hung
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
Eddie Hung
ad296d77ab
Do not rename non LUT cells in abc9
2019-06-21 17:18:04 -07:00
Eddie Hung
e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091
...
Add support for partial matches to muxcover
2019-06-21 17:13:41 -07:00
Eddie Hung
545cfbbe0d
Cope with $reduce_or common in case
2019-06-21 12:31:14 -07:00
Eddie Hung
15535112b7
Fix spacing
2019-06-21 11:52:51 -07:00
Eddie Hung
d89d663c92
Add doc
2019-06-21 11:52:28 -07:00
Eddie Hung
641b86d25f
Fix up ExclusiveDatabase with @cliffordwolf's help
2019-06-21 11:45:31 -07:00
Eddie Hung
63eb5cace9
Merge branch 'master' into eddie/muxpack
2019-06-21 11:17:19 -07:00
Clifford Wolf
ec979475e7
Replace "muxcover -freedecode" with "muxcover -dmux=cost"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 19:24:41 +02:00
Eddie Hung
6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
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Improve shregmap to handle case where first flop is common to two chains
2019-06-21 08:56:56 -07:00
Clifford Wolf
c9949dba99
Merge pull request #1117 from bwidawsk/more-home
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Add a few more filename rewrites
2019-06-21 10:13:51 +02:00
Clifford Wolf
9286b6f013
Add "muxcover -freedecode"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-21 10:02:10 +02:00
Eddie Hung
54f3237720
Fix gcc warning of potentially uninitialised
2019-06-20 22:10:43 -07:00
Clifford Wolf
891ea6512e
Improvements in muxcover
...
- Slightly under-estimate cost of decoder muxes
- Prefer larger muxes at tree root at same cost
- Don't double-count input cost for partial muxes
- Add debug log output
2019-06-20 19:47:59 -07:00
Clifford Wolf
40188457d1
Add support for partial matches to muxcover, fixes #1091
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 19:47:59 -07:00
Eddie Hung
0e97e6a00d
Fix simple_abc9/generate test with 1'bx at MSB
2019-06-20 19:41:27 -07:00
Eddie Hung
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
Eddie Hung
3f34779d64
Do not call "setundef -zero" in abc9
2019-06-20 17:38:04 -07:00
Eddie Hung
e63324f5ef
Actually, there might not be any harm in updating sigmap...
2019-06-20 17:03:05 -07:00
Eddie Hung
9c61fb0e0c
Add comment as per @cliffordwolf
2019-06-20 16:57:54 -07:00
Ben Widawsky
8767ec3fbd
Add a few more filename rewrites
...
This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"
Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-20 10:27:59 -07:00
Clifford Wolf
477e566e8d
Fix typo, fixes #1095
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 15:34:52 +02:00
Clifford Wolf
06eb87bcb7
Improve shregmap help message, fixes #1113
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 15:23:55 +02:00
Clifford Wolf
2454ad99bf
Refactor "opt_rmdff -sat"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 13:44:21 +02:00
Clifford Wolf
73bd1d59a7
Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046
2019-06-20 13:04:04 +02:00
Clifford Wolf
11ec7b2aec
Fix typo
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-20 12:23:07 +02:00
acw1251
0d888ee7ed
Fixed the help summary line for a few commands
2019-06-19 15:27:04 -04:00
Eddie Hung
96ade54993
Fix bug in #1078 , add entry to CHANGELOG
2019-06-19 09:51:11 -07:00
Clifford Wolf
3da5288ce0
Use input default values in hierarchy pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-19 11:49:20 +02:00
Eddie Hung
d80678e581
Cleanup
2019-06-17 15:10:33 -07:00
Eddie Hung
3ebba74461
Merge branch 'xaig' into xaig_dff
2019-06-17 13:51:53 -07:00
Eddie Hung
4d6d593fe3
&scorr before &sweep, remove &retime as recommended
2019-06-17 13:32:08 -07:00
Eddie Hung
a474fe937b
Merge branch 'xaig' into xaig_dff
2019-06-17 13:20:19 -07:00
Eddie Hung
63fc879a5f
Copy not move parameters/attributes
2019-06-17 13:19:45 -07:00
Eddie Hung
7dd3a7f161
Merge branch 'xaig' into xaig_dff
2019-06-17 12:58:41 -07:00
Eddie Hung
b45d06d7a3
Fix leak removing cells during ABC integration; also preserve attr
2019-06-17 12:54:24 -07:00
Eddie Hung
5ce672d1c5
Merge remote-tracking branch 'origin/xaig' into xaig_dff
2019-06-17 12:14:55 -07:00
Eddie Hung
7250c57c5a
Re-enable &dc2
2019-06-17 10:28:51 -07:00
Eddie Hung
fb90d8c18c
Cleanup
2019-06-16 09:34:26 -07:00
Eddie Hung
3ed95dae8d
Cleanup
2019-06-15 22:48:16 -07:00
Eddie Hung
416312b9ed
abc9 to recover_init by default
2019-06-15 22:44:45 -07:00
Eddie Hung
2309459605
Do not treat $__ABC_FF_ as a user cell
2019-06-15 19:36:55 -07:00
Eddie Hung
cdfb634977
Cleanup
2019-06-15 18:18:56 -07:00
Eddie Hung
c2f3f116d0
Use $__ABC_FF_ instead of $_FF_
2019-06-15 18:16:14 -07:00
Eddie Hung
a76c8a7ffd
Fix initialisation of flops
2019-06-15 09:46:35 -07:00
Eddie Hung
ac18a76beb
Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues
2019-06-15 09:34:48 -07:00
Eddie Hung
da487c4f31
For now, short $_DFF_[NP]_ from ff_map.v at re-integration
2019-06-15 09:08:18 -07:00
Eddie Hung
2d85725604
Get rid of compiler warnings
2019-06-14 13:07:56 -07:00
Eddie Hung
a632799d5b
Update abc9 -D doc
2019-06-14 12:29:46 -07:00
Eddie Hung
e391fc8e7b
Enable "abc9 -D <num>" for timing-driven synthesis
2019-06-14 12:28:01 -07:00
Eddie Hung
a48b5bfaa5
Further cleanup based on @daveshah1
2019-06-14 12:25:06 -07:00
Eddie Hung
751e640c1d
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
2019-06-14 10:29:16 -07:00
Eddie Hung
a5425a2f7e
Remove extra semicolon
2019-06-14 10:11:34 -07:00
David Shah
9566573054
ecp5: Add abc9 option
...
Signed-off-by: David Shah <dave@ds0.me>
2019-06-14 17:15:02 +01:00
Bogdan Vukobratovic
8451cbea89
Move netlist helper module to passes/opt for the time being
2019-06-14 12:14:02 +02:00
Bogdan Vukobratovic
fe651922cb
Merge remote-tracking branch 'upstream/master'
2019-06-14 12:06:57 +02:00
Bogdan Vukobratovic
53695e6729
Prepare for situation when port of the signal cannot be found
2019-06-14 11:39:24 +02:00
Bogdan Vukobratovic
291b36afeb
Some cleanup, revert sat.cc
2019-06-14 11:35:45 +02:00
Bogdan Vukobratovic
8665f48879
Implement disconnection of constant register bits
2019-06-13 19:35:37 +02:00
Eddie Hung
2c40b66785
Rip out all non FPGA stuff from abc9
2019-06-12 16:53:12 -07:00
Eddie Hung
f81a189fb8
Fix spelling
2019-06-12 16:52:09 -07:00
Eddie Hung
90dc4d82de
Revert "For 'stat' do not count modules with abc_box_id"
...
This reverts commit b89bb74452
.
2019-06-12 16:51:37 -07:00
Eddie Hung
b3faf0246d
Be more precise when connecting during ABC9 re-integration
2019-06-12 16:04:33 -07:00
Eddie Hung
2e7e73f483
Remove hacky wideports_split from abc9
2019-06-12 15:52:49 -07:00
Eddie Hung
d9974b85e7
Fix compile errors when #if 1 for debug
2019-06-12 15:47:39 -07:00
Bogdan Vukobratovic
d69989b8d2
Rename satgen_algo.h -> algo.h, code cleanup and refactoring
2019-06-12 19:35:05 +02:00
Eddie Hung
8bb67fa67c
Do not call abc9 if no outputs
2019-06-12 10:18:44 -07:00
Eddie Hung
14e870d4c4
More write_xaiger cleanup
2019-06-12 10:00:57 -07:00
Eddie Hung
b21d29598a
Consistency
2019-06-12 09:40:51 -07:00
Eddie Hung
b2c72f74f0
Merge branch 'xc7mux' into xaig
2019-06-12 09:14:27 -07:00
Eddie Hung
afd620fd5f
Typo: wire delay is -W argument
2019-06-12 09:13:53 -07:00
Eddie Hung
2cbcd6224c
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
...
This reverts commit a138381ac3
, reversing
changes made to b77c5da769
.
2019-06-12 09:05:02 -07:00
Eddie Hung
882a83c383
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
...
This reverts commit eaee250a6e
, reversing
changes made to 935df3569b
.
2019-06-12 09:04:31 -07:00
Eddie Hung
86efe9a616
Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"
...
This reverts commit 2223ca91b0
, reversing
changes made to eaee250a6e
.
2019-06-12 09:01:15 -07:00
Eddie Hung
1e838a8913
Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"
2019-06-12 08:49:15 -07:00
Eddie Hung
4c9fde87d1
Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"
...
This reverts commit 2dffa4685b
.
2019-06-12 08:48:45 -07:00
Eddie Hung
2dffa4685b
Add "-W' wire delay arg to abc9, use from synth_xilinx
2019-06-11 17:10:47 -07:00
Eddie Hung
6cdea93724
Revert "Try way that doesn't involve creating a new wire"
...
This reverts commit 2f427acc9e
.
2019-06-11 16:05:42 -07:00
Eddie Hung
d26646051c
Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux"
...
This reverts commit 5174082208
, reversing
changes made to 54379f9872
.
2019-06-11 16:05:27 -07:00
Eddie Hung
5174082208
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
2019-06-11 15:48:41 -07:00
Eddie Hung
2f427acc9e
Try way that doesn't involve creating a new wire
2019-06-11 15:48:20 -07:00
Bogdan Vukobratovic
9892df17ef
Generate satgen instance instead of calling sat pass
2019-06-11 11:47:13 +02:00
Eddie Hung
a138381ac3
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
2019-06-10 16:21:43 -07:00
Eddie Hung
f19aa8d989
If d_bit already in sigbit_chain_next, create extra wire
2019-06-10 16:16:40 -07:00
Eddie Hung
a1d4ae78a0
Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
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This reverts commit 94a5f4e609
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2019-06-10 14:34:43 -07:00
Eddie Hung
7d27e1e431
Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"
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This reverts commit 45d1bdf83a
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2019-06-10 14:34:16 -07:00
Eddie Hung
3579d68193
Revert "Refactor to ShregmapTechXilinx7Static"
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This reverts commit e1e37db860
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2019-06-10 14:34:15 -07:00
Eddie Hung
b6a39351f4
Revert "Add -tech xilinx_static"
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This reverts commit dfe9d95579
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2019-06-10 14:34:14 -07:00
Eddie Hung
e1dbeb3004
Revert "Continue support for ShregmapTechXilinx7Static"
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This reverts commit 72eda94a66
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2019-06-10 14:34:14 -07:00
Eddie Hung
9d8563178e
Revert "shregmap -tech xilinx_static to handle INIT"
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This reverts commit 935df3569b
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2019-06-10 14:34:12 -07:00
Eddie Hung
5b999ae68d
Elaborate muxpack doc
2019-06-10 10:32:19 -07:00
Eddie Hung
1dd7e23a20
Merge remote-tracking branch 'origin/master' into eddie/muxpack
2019-06-10 10:28:40 -07:00
Eddie Hung
5a46a0b385
Fine tune aigerparse
2019-06-07 16:57:32 -07:00
Eddie Hung
f705f6a0b5
Comment O(N) -> O(N^2)
2019-06-07 15:39:12 -07:00
Eddie Hung
ba52d9b471
Extend ExclusiveDatabase to query SigSpec-s (for $pmux)
2019-06-07 15:34:16 -07:00
Eddie Hung
9b408838f1
Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results
2019-06-07 14:18:17 -07:00
Eddie Hung
887df8914c
Resolve @cliffordwolf comment on redundant check
2019-06-07 11:37:52 -07:00
Eddie Hung
5ab59cd59e
Resolve @cliffordwolf comment on sigmap
2019-06-07 11:36:19 -07:00