mirror of https://github.com/YosysHQ/yosys.git
Wrong way around
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@ -659,7 +659,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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break;
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}
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if (i > 0) {
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cover("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
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cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
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cell->setPort("\\A", sig_a.extract_end(i));
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cell->setPort("\\B", sig_b.extract_end(i));
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cell->setPort("\\Y", sig_y.extract_end(i));
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@ -704,7 +704,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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break;
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}
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if (i > 0) {
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cover_list("opt.opt_expr.fine.$alu");
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cover("opt.opt_expr.fine.$alu");
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cell->setPort("\\A", sig_a.extract_end(i));
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cell->setPort("\\B", sig_b.extract_end(i));
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cell->setPort("\\X", sig_x.extract_end(i));
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