mirror of https://github.com/YosysHQ/yosys.git
ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc
This commit is contained in:
Eddie Hung
parent
4adcbecec5
commit
f42ba811b6
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@ -127,7 +127,7 @@ bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
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RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_name)
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{
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if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($concat), SHIFT_OPS) && port_name == ID(B))
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if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($concat), SHIFT_OPS) && port_name == ID::B)
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return port_name;
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return "";
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@ -135,9 +135,9 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na
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RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) {
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if (cell->type == ID($alu) && port_name == ID(B))
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if (cell->type == ID($alu) && port_name == ID::B)
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return cell->getPort(ID(BI));
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else if (cell->type == ID($sub) && port_name == ID(B))
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else if (cell->type == ID($sub) && port_name == ID::B)
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return RTLIL::Const(1, 1);
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return RTLIL::Const(0, 1);
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@ -173,9 +173,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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for (const auto& p : ports) {
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auto op = p.op;
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RTLIL::IdString muxed_port_name = ID(A);
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if (decode_port(op, ID(A), &assign_map) == operand)
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muxed_port_name = ID(B);
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RTLIL::IdString muxed_port_name = ID::A;
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if (decode_port(op, ID::A, &assign_map) == operand)
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muxed_port_name = ID::B;
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auto operand = decode_port(op, muxed_port_name, &assign_map);
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if (operand.sig.size() > max_width)
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@ -204,9 +204,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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if (muxed_op.sign != muxed_operands[0].sign)
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muxed_op = ExtSigSpec(module->Neg(NEW_ID, muxed_op.sig, muxed_op.is_signed));
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RTLIL::SigSpec mux_y = mux->getPort(ID(Y));
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RTLIL::SigSpec mux_a = mux->getPort(ID(A));
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RTLIL::SigSpec mux_b = mux->getPort(ID(B));
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RTLIL::SigSpec mux_y = mux->getPort(ID::Y);
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RTLIL::SigSpec mux_a = mux->getPort(ID::A);
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RTLIL::SigSpec mux_b = mux->getPort(ID::B);
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RTLIL::SigSpec mux_s = mux->getPort(ID(S));
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RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width);
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@ -216,24 +216,24 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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int conn_width = ports[0].sig.size();
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int conn_offset = ports[0].mux_port_offset;
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shared_op->setPort(ID(Y), shared_op->getPort(ID(Y)).extract(0, conn_width));
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shared_op->setPort(ID::Y, shared_op->getPort(ID::Y).extract(0, conn_width));
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if (mux->type == ID($pmux)) {
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shared_pmux_s = RTLIL::SigSpec();
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for (const auto &p : ports) {
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shared_pmux_s.append(mux_s[p.mux_port_id]);
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mux_b.replace(p.mux_port_id * mux_a.size() + conn_offset, shared_op->getPort(ID(Y)));
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mux_b.replace(p.mux_port_id * mux_a.size() + conn_offset, shared_op->getPort(ID::Y));
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}
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} else {
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shared_pmux_s = RTLIL::SigSpec{mux_s, module->Not(NEW_ID, mux_s)};
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mux_a.replace(conn_offset, shared_op->getPort(ID(Y)));
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mux_b.replace(conn_offset, shared_op->getPort(ID(Y)));
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mux_a.replace(conn_offset, shared_op->getPort(ID::Y));
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mux_b.replace(conn_offset, shared_op->getPort(ID::Y));
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}
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mux->setPort(ID(A), mux_a);
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mux->setPort(ID(B), mux_b);
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mux->setPort(ID(Y), mux_y);
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mux->setPort(ID::A, mux_a);
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mux->setPort(ID::B, mux_b);
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mux->setPort(ID::Y, mux_y);
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mux->setPort(ID(S), mux_s);
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for (const auto &op : muxed_operands)
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@ -251,11 +251,11 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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shared_op->setParam(ID(Y_WIDTH), conn_width);
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if (decode_port(shared_op, ID(A), &assign_map) == operand) {
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shared_op->setPort(ID(B), mux_to_oper);
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if (decode_port(shared_op, ID::A, &assign_map) == operand) {
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shared_op->setPort(ID::B, mux_to_oper);
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shared_op->setParam(ID(B_WIDTH), max_width);
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} else {
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shared_op->setPort(ID(A), mux_to_oper);
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shared_op->setPort(ID::A, mux_to_oper);
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shared_op->setParam(ID(A_WIDTH), max_width);
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}
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}
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@ -286,9 +286,9 @@ void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpe
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auto p = *it;
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auto op = p->op;
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RTLIL::IdString muxed_port_name = ID(A);
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if (decode_port(op, ID(A), &assign_map) == shared_operand) {
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muxed_port_name = ID(B);
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RTLIL::IdString muxed_port_name = ID::A;
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if (decode_port(op, ID::A, &assign_map) == shared_operand) {
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muxed_port_name = ID::B;
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}
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auto operand = decode_port(op, muxed_port_name, &assign_map);
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@ -315,7 +315,7 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxCon
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auto op_a = seed->op;
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for (RTLIL::IdString port_name : {ID(A), ID(B)}) {
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for (RTLIL::IdString port_name : {ID::A, ID::B}) {
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oper = decode_port(op_a, port_name, &assign_map);
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auto operand_users = operand_to_users.at(oper);
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@ -355,7 +355,7 @@ dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, d
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std::function<void(RTLIL::SigBit)> remove_outsig_from_aux_bit = [&](RTLIL::SigBit auxbit) {
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auto aux_outsig = op_aux_to_outsig.at(auxbit);
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auto op = outsig_to_operator.at(aux_outsig);
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auto op_outsig = assign_map(op->getPort(ID(Y)));
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auto op_outsig = assign_map(op->getPort(ID::Y));
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remove_outsig(op_outsig);
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for (auto aux_outbit : aux_outsig)
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@ -367,11 +367,11 @@ dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, d
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int mux_port_size;
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if (mux->type.in(ID($mux), ID($_MUX_))) {
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mux_port_size = mux->getPort(ID(A)).size();
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sig = RTLIL::SigSpec{mux->getPort(ID(B)), mux->getPort(ID(A))};
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mux_port_size = mux->getPort(ID::A).size();
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sig = RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)};
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} else {
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mux_port_size = mux->getPort(ID(A)).size();
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sig = mux->getPort(ID(B));
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mux_port_size = mux->getPort(ID::A).size();
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sig = mux->getPort(ID::B);
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}
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auto mux_insig = assign_map(sig);
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@ -510,12 +510,12 @@ struct OptSharePass : public Pass {
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}
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}
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auto mux_insig = assign_map(cell->getPort(ID(Y)));
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auto mux_insig = assign_map(cell->getPort(ID::Y));
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outsig_to_operator[mux_insig] = cell;
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for (auto outbit : mux_insig)
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op_outbit_to_outsig[outbit] = mux_insig;
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for (RTLIL::IdString port_name : {ID(A), ID(B)}) {
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for (RTLIL::IdString port_name : {ID::A, ID::B}) {
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auto op_insig = decode_port(cell, port_name, &assign_map);
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op_insigs.push_back(op_insig);
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operand_to_users[op_insig].insert(cell);
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