mirror of https://github.com/YosysHQ/yosys.git
Trim shiftx_width when upper bits are 1'bx
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@ -164,6 +164,11 @@ endmatch
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code shiftx_width
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shiftx_width = param(shiftx, \A_WIDTH).as_int();
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while (shiftx_width > 1) {
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if (port(shiftx, \A)[shiftx_width-1] != State::Sx)
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break;
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--shiftx_width;
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}
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endcode
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match first
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@ -177,7 +182,7 @@ code
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chain.push_back(first);
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subpattern(tail);
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finally
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if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int())
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if (GetSize(chain) == shiftx_width)
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accept;
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chain.clear();
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endcode
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