riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix compile error

This commit is contained in:
Eddie Hung 2019-08-07 14:31:55 -07:00
parent a206aed977
commit fb568ddb4e
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
passes/pmgen/ice40_dsp.cc
View File

@ -224,11 +224,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
pm.autoremove(st.ffH);
pm.autoremove(st.addAB);
if (st.ffO_lo) {
SigSpec O = st.sigO.extract(0,GetSize(st.ffO_lo));
SigSpec O = st.sigO.extract(0,st.ffO_lo->getParam("\\WIDTH").as_int());
st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
}
if (st.ffO_hi) {
SigSpec O = st.sigO.extract(16,GetSize(st.ffo_hi));
SigSpec O = st.sigO.extract(16,st.ffO_hi->getParam("\\WIDTH").as_int());
st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
}
}