riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Improve ice40_dsp for non-fully-32-bit adders

This commit is contained in:
Eddie Hung 2019-08-09 17:23:12 -07:00
parent 6d254f2de8
commit 3dd3ab98c2
1 changed files with 8 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
passes/pmgen/ice40_dsp.pmg
View File

@ -106,7 +106,9 @@ endcode
match addA
select addA->type.in($add)
select nusers(port(addA, \A)) == 2
index <SigSpec> port(addA, \A) === sigH
filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH)
//index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int())
filter port(addA, \A) == sigH.extract(0, param(addA, \A_WIDTH).as_int())
optional
endmatch
@ -114,7 +116,9 @@ match addB
if !addA
select addB->type.in($add, $sub)
select nusers(port(addB, \B)) == 2
index <SigSpec> port(addB, \B) === sigH
filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH)
//index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int())
filter port(addB, \B) == sigH.extract(0, param(addB, \B_WIDTH).as_int())
optional
endmatch
@ -144,7 +148,8 @@ code addAB sigCD sigO
if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
reject;
if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
// If accumulator, check adder width and signedness
if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
reject;
sigO = port(addAB, \Y);