mirror of https://github.com/YosysHQ/yosys.git
Initial progress on xilinx_srl
This commit is contained in:
Eddie Hung
parent
7d8db1c053
commit
0250712486
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@ -30,3 +30,9 @@ PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg
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passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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$(P) mkdir -p passes/pmgen && python3 $< -o $@ -p peepopt $(filter-out $<,$^)
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# --------------------------------------
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OBJS += passes/pmgen/xilinx_srl.o
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passes/pmgen/xilinx_srl.o: passes/pmgen/xilinx_srl_pm.h
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$(eval $(call add_extra_objs,passes/pmgen/xilinx_srl_pm.h))
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@ -0,0 +1,115 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// for peepopt_pm
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bool did_something;
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#include "passes/pmgen/xilinx_srl_pm.h"
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#include "passes/pmgen/ice40_dsp_pm.h"
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#include "passes/pmgen/peepopt_pm.h"
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void reduce_chain(xilinx_srl_pm &pm, int minlen)
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{
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auto &st = pm.st_reduce;
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auto &ud = pm.ud_reduce;
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if (GetSize(ud.longest_chain) < minlen)
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return;
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log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
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auto last_cell = ud.longest_chain.back();
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for (auto cell : ud.longest_chain) {
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log_debug(" %s\n", log_id(cell));
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if (cell != last_cell)
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pm.autoremove(cell);
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}
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Cell *c = last_cell;
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SigSpec Q = st.first->getPort(ID(Q));
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c->setPort(ID(Q), Q);
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if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
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c->parameters.clear();
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c->setParam(ID(DEPTH), GetSize(ud.longest_chain));
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// TODO c->setParam(ID(INIT), init);
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if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
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c->setParam(ID(CLKPOL), 1);
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else
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log_abort();
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if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
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c->setParam(ID(ENPOL), 1);
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else if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PN_)))
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c->setParam(ID(ENPOL), 0);
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else
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c->setParam(ID(ENPOL), 2);
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if (c->type.in(ID($_DFF_N_), ID($_DFF_P_)))
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c->setPort(ID(E), State::S1);
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c->setPort(ID(L), GetSize(ud.longest_chain)-1);
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c->type = ID($__XILINX_SHREG_);
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}
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else
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log_abort();
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log(" -> %s (%s)\n", log_id(c), log_id(c->type));
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}
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struct XilinxSrlPass : public Pass {
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XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" xilinx_srl [options] [selection]\n");
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log("\n");
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log("TODO.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");
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int minlen = 3;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
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minlen = atoi(args[++argidx].c_str());
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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auto f = std::bind(reduce_chain, std::placeholders::_1, minlen);
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for (auto module : design->selected_modules())
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while (xilinx_srl_pm(module, module->selected_cells()).run_reduce(f)) {}
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}
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} XilinxSrlPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,92 @@
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pattern reduce
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udata <vector<Cell*>> chain longest_chain
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udata <pool<Cell*>> non_first_cells
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code
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non_first_cells.clear();
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subpattern(setup);
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endcode
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match first
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select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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filter !non_first_cells.count(first)
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//generate
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// SigSpec A = module->addWire(NEW_ID);
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// SigSpec B = module->addWire(NEW_ID);
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// SigSpec Y = module->addWire(NEW_ID);
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// switch (rng(3))
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// {
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// case 0:
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// module->addAndGate(NEW_ID, A, B, Y);
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// break;
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// case 1:
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// module->addOrGate(NEW_ID, A, B, Y);
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// break;
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// case 2:
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// module->addXorGate(NEW_ID, A, B, Y);
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// break;
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// }
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endmatch
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code
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longest_chain.clear();
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chain.push_back(first);
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subpattern(tail);
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finally
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chain.pop_back();
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log_assert(chain.empty());
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if (GetSize(longest_chain) > 1)
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accept;
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endcode
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// ------------------------------------------------------------------
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subpattern setup
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match first
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select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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endmatch
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match next
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select nusers(port(next, \Q)) == 2
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select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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index <IdString> next->type === first->type
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index <SigSpec> port(next, \Q) === port(first, \D)
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endmatch
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code
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non_first_cells.insert(next);
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endcode
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// ------------------------------------------------------------------
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subpattern tail
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arg first
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match next
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semioptional
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select nusers(port(next, \Q)) == 2
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select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
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index <IdString> next->type === chain.back()->type
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index <SigSpec> port(next, \Q) === port(chain.back(), \D)
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//generate 10
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// SigSpec A = module->addWire(NEW_ID);
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// SigSpec B = module->addWire(NEW_ID);
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// SigSpec Y = port(chain.back().first, chain.back().second);
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// Cell *c = module->addAndGate(NEW_ID, A, B, Y);
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// c->type = chain.back().first->type;
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endmatch
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code
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if (next) {
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chain.push_back(next);
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subpattern(tail);
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} else {
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if (GetSize(chain) > GetSize(longest_chain))
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longest_chain = chain;
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}
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finally
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if (next)
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chain.pop_back();
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endcode
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