mirror of https://github.com/YosysHQ/yosys.git
Cleanup
This commit is contained in:
Eddie Hung
parent
0b5b56c1ec
commit
e83f231927
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@ -21,8 +21,8 @@ code sigH
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endcode
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match ffA
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if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
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select ffA->type.in($dff)
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filter mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
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filter !port(mul, \A).remove_const().empty()
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filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
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optional
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@ -44,8 +44,8 @@ code sigA clock clock_pol
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endcode
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match ffB
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if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
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select ffB->type.in($dff)
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filter mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
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filter !port(mul, \B).remove_const().empty()
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filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
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optional
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@ -73,11 +73,11 @@ code sigB clock clock_pol
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endcode
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match ffH
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if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
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select ffH->type.in($dff)
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select nusers(port(ffH, \D)) == 2
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index <SigSpec> port(ffH, \D) === sigH
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// Ensure pipeline register is not already used
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filter mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
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optional
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endmatch
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@ -154,7 +154,7 @@ endcode
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match muxA
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select muxA->type.in($mux)
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select nusers(port(muxA, \A)) == 2
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index <int> nusers(port(muxA, \A)) === 2
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index <SigSpec> port(muxA, \A) === sigO
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optional
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endmatch
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@ -162,7 +162,7 @@ endmatch
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match muxB
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if !muxA
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select muxB->type.in($mux)
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select nusers(port(muxB, \B)) == 2
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index <int> nusers(port(muxB, \B)) === 2
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index <SigSpec> port(muxB, \B) === sigO
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optional
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endmatch
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@ -185,16 +185,16 @@ code sigOused
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endcode
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match ffO_lo
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if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2
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select ffO_lo->type.in($dff)
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filter nusers(sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()))) == 2
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filter includes(port(ffO_lo, \D).to_sigbit_set(), sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int())).remove_const().to_sigbit_set())
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optional
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endmatch
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match ffO_hi
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if GetSize(sigOused) > 16
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if nusers(sigOused.extract_end(16)) == 2
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select ffO_hi->type.in($dff)
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filter GetSize(sigOused) > 16
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filter nusers(sigOused.extract_end(16)) == 2
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filter includes(port(ffO_hi, \D).to_sigbit_set(), sigOused.extract_end(16).remove_const().to_sigbit_set())
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optional
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endmatch
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@ -9,11 +9,11 @@ match dsp
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endmatch
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match ffA
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if param(dsp, \AREG).as_int() == 0
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if !port(dsp, \A).remove_const().empty()
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select ffA->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffA, \CLK_POLARITY).as_bool()
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filter param(dsp, \AREG).as_int() == 0
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filter !port(dsp, \A).remove_const().empty()
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filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set())
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optional
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endmatch
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@ -24,11 +24,11 @@ code clock
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endcode
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match ffB
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if param(dsp, \BREG).as_int() == 0
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if !port(dsp, \B).remove_const().empty()
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select ffB->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffB, \CLK_POLARITY).as_bool()
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filter param(dsp, \BREG).as_int() == 0
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filter !port(dsp, \B).remove_const().empty()
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filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set())
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optional
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endmatch
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@ -51,9 +51,9 @@ endcode
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match addA
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select addA->type.in($add)
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select param(addA, \A_SIGNED).as_bool() && param(addA, \B_SIGNED).as_bool()
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select nusers(port(addA, \A)) == 2
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index <int> nusers(port(addA, \A)) === 2
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//index <SigSpec> port(addA, \A) === sigP.extract(0, param(addA, \A_WIDTH).as_int())
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filter GetSize(sigP) >= param(addA, \A_WIDTH).as_int()
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filter param(addA, \A_WIDTH).as_int() <= GetSize(sigP)
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filter port(addA, \A) == sigP.extract(0, param(addA, \A_WIDTH).as_int())
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optional
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endmatch
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@ -62,9 +62,9 @@ match addB
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if !addA
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select addB->type.in($add, $sub)
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select param(addB, \A_SIGNED).as_bool() && param(addB, \B_SIGNED).as_bool()
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select nusers(port(addB, \B)) == 2
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index <int> nusers(port(addB, \B)) === 2
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//index <SigSpec> port(addB, \B) === sigP.extract(0, param(addB, \B_WIDTH).as_int())
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filter GetSize(sigP) >= param(addB, \B_WIDTH).as_int()
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filter param(addB, \B_WIDTH).as_int() <= GetSize(sigP)
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filter port(addB, \B) == sigP.extract(0, param(addB, \B_WIDTH).as_int())
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optional
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endmatch
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@ -110,12 +110,12 @@ code sigPused
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endcode
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match ffP
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if param(dsp, \PREG).as_int() == 0
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if !sigPused.empty()
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select ffP->type.in($dff)
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select nusers(port(ffP, \D)) == 2
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index <int> nusers(port(ffP, \D)) === 2
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// DSP48E1 does not support clock inversion
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select param(ffP, \CLK_POLARITY).as_bool()
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filter param(dsp, \PREG).as_int() == 0
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filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
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filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
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optional
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