mirror of https://github.com/YosysHQ/yosys.git
proc_prune: Promote partially redundant assignments.
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@ -82,14 +82,23 @@ struct PruneWorker
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if (root) {
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bool promotable = true;
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for (auto &bit : lhs) {
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if (bit.wire && affected[bit]) {
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if (bit.wire && affected[bit] && !assigned[bit]) {
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promotable = false;
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break;
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}
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}
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if (promotable) {
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RTLIL::SigSpec rhs = sigmap(it->second);
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RTLIL::SigSig conn;
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for (int i = 0; i < GetSize(lhs); i++) {
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RTLIL::SigBit lhs_bit = lhs[i];
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if (lhs_bit.wire && !assigned[lhs_bit]) {
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conn.first.append_bit(lhs_bit);
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conn.second.append(rhs.extract(i));
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}
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}
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promoted_count++;
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module->connect(*it);
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module->connect(conn);
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remove.insert(*it);
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}
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}
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