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xilinx_dsp to be sensitive to keep attribute

This commit is contained in:
Eddie Hung 2019-08-15 12:34:11 -07:00
parent 96ee7b9cf7
commit c320abc3f4
1 changed files with 14 additions and 1 deletions
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15
passes/pmgen/xilinx_dsp.pmg
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@ -29,8 +29,13 @@ match ffA
endmatch
code clock
if (ffA)
if (ffA) {
clock = port(ffA, \CLK).as_bit();
for (auto b : port(ffA, \Q))
if (b.wire->get_bool_attribute(\keep))
reject;
}
endcode
match ffB
@ -45,6 +50,10 @@ endmatch
code clock
if (ffB) {
for (auto b : port(ffB, \Q))
if (b.wire->get_bool_attribute(\keep))
reject;
SigBit c = port(ffB, \CLK).as_bit();
if (clock != SigBit() && c != clock)
@ -156,6 +165,10 @@ code ffP clock
// ffP = ffY;
if (ffP) {
for (auto b : port(ffP, \Q))
if (b.wire->get_bool_attribute(\keep))
reject;
SigBit c = port(ffP, \CLK).as_bit();
if (clock != SigBit() && c != clock)