mirror of https://github.com/YosysHQ/yosys.git
Refactor demo_reduce into test_pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
parent
016036f247
commit
4a57b7e1ab
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@ -1,3 +1,3 @@
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/demo_reduce_pm.h
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/test_pmgen_pm.h
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/ice40_dsp_pm.h
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/peepopt_pm.h
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@ -9,9 +9,9 @@ $(eval $(call add_extra_objs,passes/pmgen/ice40_dsp_pm.h))
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# --------------------------------------
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OBJS += passes/pmgen/demo_reduce.o
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passes/pmgen/demo_reduce.o: passes/pmgen/demo_reduce_pm.h
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$(eval $(call add_extra_objs,passes/pmgen/demo_reduce_pm.h))
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OBJS += passes/pmgen/test_pmgen.o
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passes/pmgen/test_pmgen.o: passes/pmgen/test_pmgen_pm.h
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$(eval $(call add_extra_objs,passes/pmgen/test_pmgen_pm.h))
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# --------------------------------------
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@ -23,9 +23,9 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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#include "passes/pmgen/demo_reduce_pm.h"
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#include "passes/pmgen/test_pmgen_pm.h"
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void create_reduce(demo_reduce_pm &pm)
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void reduce_chain(test_pmgen_pm &pm)
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{
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auto &st = pm.st_reduce;
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auto &ud = pm.ud_reduce;
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@ -65,23 +65,58 @@ void create_reduce(demo_reduce_pm &pm)
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log(" -> %s (%s)\n", log_id(c), log_id(c->type));
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}
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struct DemoReducePass : public Pass {
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DemoReducePass() : Pass("demo_reduce", "map chains of AND/OR/XOR") { }
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void reduce_tree(test_pmgen_pm &pm)
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{
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auto &st = pm.st_reduce;
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auto &ud = pm.ud_reduce;
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if (ud.longest_chain.empty())
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return;
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SigSpec A = ud.leaves;
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SigSpec Y = st.first->getPort(ID(Y));
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pm.autoremove(st.first);
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log("Found %s tree with %d leaves for %s (%s).\n", log_id(st.first->type),
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GetSize(A), log_signal(Y), log_id(st.first));
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Cell *c;
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if (st.first->type == ID($_AND_))
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c = pm.module->addReduceAnd(NEW_ID, A, Y);
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else if (st.first->type == ID($_OR_))
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c = pm.module->addReduceOr(NEW_ID, A, Y);
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else if (st.first->type == ID($_XOR_))
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c = pm.module->addReduceXor(NEW_ID, A, Y);
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else
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log_abort();
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log(" -> %s (%s)\n", log_id(c), log_id(c->type));
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}
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struct TestPmgenPass : public Pass {
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TestPmgenPass() : Pass("test_pmgen", "test pass for pmgen") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" demo_reduce [options] [selection]\n");
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log(" test_pmgen -reduce_chain [options] [selection]\n");
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log("\n");
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log("Demo for recursive pmgen patterns. Map chains of AND/OR/XOR to $reduce_*.\n");
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log("\n");
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log("\n");
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log(" test_pmgen -reduce_tree [options] [selection]\n");
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log("\n");
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log("Demo for recursive pmgen patterns. Map trees of AND/OR/XOR to $reduce_*.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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void execute_reduce_chain(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header(design, "Executing DEMO_REDUCE pass.\n");
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log_header(design, "Executing TEST_PMGEN pass (-reduce_chain).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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for (argidx = 2; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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@ -92,8 +127,39 @@ struct DemoReducePass : public Pass {
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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demo_reduce_pm(module, module->selected_cells()).run_reduce(create_reduce);
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test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_chain);
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}
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} DemoReducePass;
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void execute_reduce_tree(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header(design, "Executing TEST_PMGEN pass (-reduce_tree).\n");
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size_t argidx;
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for (argidx = 2; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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test_pmgen_pm(module, module->selected_cells()).run_reduce(reduce_tree);
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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if (GetSize(args) > 1)
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{
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if (args[1] == "-reduce_chain")
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return execute_reduce_chain(args, design);
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if (args[1] == "-reduce_tree")
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return execute_reduce_tree(args, design);
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}
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log_cmd_error("Missing or unsupported mode parameter.\n");
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}
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} TestPmgenPass;
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PRIVATE_NAMESPACE_END
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@ -3,6 +3,7 @@ pattern reduce
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state <IdString> portname
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udata <vector<pair<Cell*, IdString>>> chain longest_chain
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udata <pool<Cell*>> non_first_cells
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udata <SigSpec> leaves
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code
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non_first_cells.clear();
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@ -15,6 +16,7 @@ match first
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endmatch
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code
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leaves = SigSpec();
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longest_chain.clear();
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chain.push_back(make_pair(first, \A));
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subpattern(tail);
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@ -73,6 +75,7 @@ code
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} else {
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if (GetSize(chain) > GetSize(longest_chain))
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longest_chain = chain;
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leaves.append(port(chain.back().first, chain.back().second));
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}
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finally
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if (next)
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