mirror of https://github.com/YosysHQ/yosys.git
proc_prune: fix handling of exactly identical assigns.
Before this commit, in a process like: process $proc$bug.v:8$3 assign $foo \bar switch \sel case 1'1 assign $foo 1'1 assign $foo 1'1 case assign $foo 1'0 end end both of the "assign $foo 1'1" would incorrectly be removed. Fixes #1243.
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3414ee1e3f
commit
0b09a347dc
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@ -65,8 +65,7 @@ struct PruneWorker
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pool<RTLIL::SigBit> sw_assigned = do_switch((*it), assigned, affected);
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assigned.insert(sw_assigned.begin(), sw_assigned.end());
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}
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pool<RTLIL::SigSig> remove;
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for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ++it) {
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for (auto it = cs->actions.rbegin(); it != cs->actions.rend(); ) {
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RTLIL::SigSpec lhs = sigmap(it->first);
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bool redundant = true;
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for (auto &bit : lhs) {
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@ -75,9 +74,10 @@ struct PruneWorker
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break;
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}
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}
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bool remove = false;
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if (redundant) {
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removed_count++;
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remove.insert(*it);
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remove = true;
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} else {
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if (root) {
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bool promotable = true;
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@ -99,7 +99,7 @@ struct PruneWorker
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}
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promoted_count++;
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module->connect(conn);
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remove.insert(*it);
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remove = true;
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}
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}
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for (auto &bit : lhs)
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@ -109,11 +109,9 @@ struct PruneWorker
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if (bit.wire)
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affected.insert(bit);
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}
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}
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for (auto it = cs->actions.begin(); it != cs->actions.end(); ) {
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if (remove[*it]) {
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it = cs->actions.erase(it);
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} else it++;
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if (remove)
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cs->actions.erase((it++).base() - 1);
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else it++;
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}
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return assigned;
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}
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