mirror of https://github.com/YosysHQ/yosys.git
Disable $dffe
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57b2e4b9c1
commit
911129e3ef
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@ -58,11 +58,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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SigSpec Q = st.ffA->getPort("\\Q");
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A.replace(Q, D);
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cell->setPort("\\A", A);
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cell->setParam("\\AREG", State::S1);
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cell->setParam("\\AREG", 1);
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if (st.ffA->type == "$dff")
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cell->setPort("\\CEA2", State::S1);
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else if (st.ffA->type == "$dffe")
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cell->setPort("\\CEA2", st.ffA->getPort("\\EN"));
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//else if (st.ffA->type == "$dffe")
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// cell->setPort("\\CEA2", st.ffA->getPort("\\EN"));
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else log_abort();
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}
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if (st.ffB) {
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@ -71,11 +71,11 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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SigSpec Q = st.ffB->getPort("\\Q");
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B.replace(Q, D);
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cell->setPort("\\B", B);
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cell->setParam("\\BREG", State::S1);
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cell->setParam("\\BREG", 1);
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if (st.ffB->type == "$dff")
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cell->setPort("\\CEB2", State::S1);
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else if (st.ffB->type == "$dffe")
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cell->setPort("\\CEB2", st.ffB->getPort("\\EN"));
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//else if (st.ffB->type == "$dffe")
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// cell->setPort("\\CEB2", st.ffB->getPort("\\EN"));
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else log_abort();
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}
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if (st.ffP) {
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@ -91,8 +91,8 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
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cell->setParam("\\PREG", State::S1);
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if (st.ffP->type == "$dff")
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cell->setPort("\\CEP", State::S1);
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else if (st.ffP->type == "$dffe")
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cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
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//else if (st.ffP->type == "$dffe")
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// cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
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else log_abort();
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st.ffP->connections_.at("\\Q").replace(P, pm.module->addWire(NEW_ID, GetSize(P)));
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