mirror of https://github.com/YosysHQ/yosys.git
parent
747690a6df
commit
82cbfada1b
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@ -143,7 +143,7 @@ code addAB sigCD sigO
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if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
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reject;
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if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \B_SIGNED).as_bool()))
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if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
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reject;
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sigO = port(addAB, \Y);
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