mirror of https://github.com/YosysHQ/yosys.git
Do not SigSpec::extract() beyond bounds
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@ -224,11 +224,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
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pm.autoremove(st.ffH);
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pm.autoremove(st.addAB);
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if (st.ffO_lo) {
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SigSpec O = st.sigO.extract(0,16);
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SigSpec O = st.sigO.extract(0,GetSize(st.ffO_lo));
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st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
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}
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if (st.ffO_hi) {
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SigSpec O = st.sigO.extract(16,16);
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SigSpec O = st.sigO.extract(16,GetSize(st.ffo_hi));
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st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
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}
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}
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@ -156,15 +156,17 @@ endcode
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match ffO_lo
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select ffO_lo->type.in($dff)
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filter nusers(sigO.extract(0,16)) == 2
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filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,16).to_sigbit_set())
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filter GetSize(sigO) >= param(ffO_lo, \WIDTH).as_int()
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filter nusers(sigO.extract(0,param(ffO_lo, \WIDTH).as_int())) == 2
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filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,param(ffO_lo, \WIDTH).as_int()).to_sigbit_set())
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optional
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endmatch
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match ffO_hi
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select ffO_hi->type.in($dff)
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filter nusers(sigO.extract(16,16)) == 2
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filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,16).to_sigbit_set())
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filter GetSize(sigO) >= 16+param(ffO_hi, \WIDTH).as_int()
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filter nusers(sigO.extract(16,param(ffO_hi, \WIDTH).as_int())) == 2
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filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,param(ffO_hi, \WIDTH).as_int()).to_sigbit_set())
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optional
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endmatch
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@ -184,7 +186,7 @@ code clock clock_pol sigO sigCD
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clock = c;
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clock_pol = cp;
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if (port(ffO_lo, \Q) != sigO.extract(0,16))
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if (port(ffO_lo, \Q) != sigO.extract(0,param(ffO_lo, \WIDTH).as_int()))
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sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
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}
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@ -202,7 +204,7 @@ code clock clock_pol sigO sigCD
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clock = c;
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clock_pol = cp;
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if (port(ffO_hi, \Q) != sigO.extract(16,16))
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if (port(ffO_hi, \Q) != sigO.extract(16,param(ffO_hi, \WIDTH).as_int()))
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sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
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}
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