riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Revert "Trim shiftx_width when upper bits are 1'bx" 

This reverts commit 7e7965ca7b.
This commit is contained in:
Eddie Hung 2019-08-21 19:18:27 -07:00
parent c7859531c2
commit 5c8344363f
1 changed files with 1 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
passes/pmgen/xilinx_srl.pmg
View File

@ -164,11 +164,6 @@ endmatch
code shiftx_width
shiftx_width = param(shiftx, \A_WIDTH).as_int();
while (shiftx_width > 1) {
if (port(shiftx, \A)[shiftx_width-1] != State::Sx)
break;
--shiftx_width;
}
endcode
match first
@ -182,7 +177,7 @@ code
chain.push_back(first);
subpattern(tail);
finally
if (GetSize(chain) == shiftx_width)
if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int())
accept;
chain.clear();
endcode