tangxifan
|
0b8473e960
|
start developing graphs for muxes, with aims to simplify netlist and bitstream generation
|
2019-08-20 15:24:52 -06:00 |
tangxifan
|
aa7f3bef7f
|
fixed bugs in configure pb_rr_graph and dependence on testbenches
|
2019-08-16 18:20:30 -06:00 |
tangxifan
|
e456b6f905
|
replace spice_models with circuit model in bitstream generator
|
2019-08-16 16:36:49 -06:00 |
tangxifan
|
5ece7ab6d0
|
start refactoring the bitstream part using spice_models
|
2019-08-16 15:58:14 -06:00 |
tangxifan
|
b66e120366
|
patch on local encoders for unused configuration, avoid chip-burn issues
|
2019-08-16 15:32:23 -06:00 |
tangxifan
|
4eb046760b
|
still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
|
2019-08-15 21:57:59 -06:00 |
AurelienUoU
|
df873903f8
|
Bug fix for non fracturable LUT
|
2019-08-14 09:32:15 -06:00 |
tangxifan
|
d2d8af5416
|
bug fixing for pb_type num_conf_bits and num_iopads stats
|
2019-08-13 17:34:09 -06:00 |
tangxifan
|
edfa72a666
|
try to fix the bug in clock net identification
|
2019-08-13 16:47:28 -06:00 |
tangxifan
|
1118b28397
|
use single subckt for switch box again, to abolish the multi-module subckt
|
2019-08-13 16:11:04 -06:00 |
tangxifan
|
4cffd8ac2d
|
keep route file updated with tileable rr_graph
|
2019-08-13 15:37:42 -06:00 |
tangxifan
|
c7526cb43c
|
memory sanitized
|
2019-08-13 14:19:40 -06:00 |
tangxifan
|
ef4d15df4e
|
reorganize the libarchfpga repository
|
2019-08-13 13:37:35 -06:00 |
tangxifan
|
392f579836
|
add linking functions for circuit models and architecture, memory sanitizing is ongoing
|
2019-08-13 13:25:23 -06:00 |
tangxifan
|
c004699a14
|
complete parsers for ports
|
2019-08-09 21:00:41 -06:00 |
tangxifan
|
74da4ed51a
|
start creating the class for circuit models
|
2019-08-07 11:38:45 -06:00 |
tangxifan
|
f57495feba
|
Now we can also auto-generate the Verilog for a mux2 std cell
|
2019-08-06 15:19:01 -06:00 |
tangxifan
|
afa468a442
|
hotfix in minor Verilog generation
|
2019-08-06 14:17:57 -06:00 |
tangxifan
|
b4f3dfc82d
|
bug fixing for local encoder's bitstream generation
|
2019-08-06 14:17:57 -06:00 |
tangxifan
|
3a490fdd59
|
bug fixing on the port map alignment
|
2019-08-06 14:17:56 -06:00 |
tangxifan
|
890ff05628
|
bug fixing and get ready for testing
|
2019-08-06 14:17:56 -06:00 |
tangxifan
|
c08c136844
|
set a working range for the encoders
|
2019-08-06 14:17:56 -06:00 |
tangxifan
|
386bddacd1
|
updated bitstream generator for local encoders
|
2019-08-06 14:17:56 -06:00 |
tangxifan
|
557b1af633
|
add Verilog generation for local encoders, bitstream upgrade TODO
|
2019-08-06 14:17:56 -06:00 |
tangxifan
|
003883b13b
|
implementing the local encoders
|
2019-08-06 14:17:55 -06:00 |
tangxifan
|
fb2ca66ce9
|
start adding submodules of local encoders to multiplexer
|
2019-08-06 14:17:55 -06:00 |
tangxifan
|
32e3a556b9
|
bug fixing herited from explicit mapping
|
2019-07-17 09:26:05 -06:00 |
tangxifan
|
8b8e18a8de
|
bug fixing for mux subckt names
|
2019-07-17 08:59:57 -06:00 |
tangxifan
|
a2505ff16a
|
turn on std cell explicit port map
|
2019-07-17 08:36:09 -06:00 |
tangxifan
|
dcc96bf7f5
|
bug fixing
|
2019-07-17 08:25:52 -06:00 |
tangxifan
|
6e1d49d74e
|
start to support direct mapping to MUX2 standard cells
|
2019-07-17 07:54:23 -06:00 |
tangxifan
|
e9154b1f74
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-16 14:42:45 -06:00 |
tangxifan
|
115411941b
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-16 13:15:45 -06:00 |
Baudouin Chauviere
|
69014704ef
|
Explicit verilog final push
|
2019-07-16 13:13:30 -06:00 |
Baudouin Chauviere
|
e602006a07
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
|
2019-07-16 12:45:13 -06:00 |
AurelienUoU
|
35e1962732
|
Merge branch 'dev' into documentation
|
2019-07-15 21:19:26 -06:00 |
AurelienUoU
|
1cf4e78502
|
Update documentation and help
|
2019-07-15 21:16:15 -06:00 |
tangxifan
|
bcc6346533
|
speeding up identifying unique modules in routing
|
2019-07-14 13:49:20 -06:00 |
tangxifan
|
4c6e245885
|
speed-up the unique routing process
|
2019-07-14 12:22:00 -06:00 |
tangxifan
|
b690e702f6
|
adding more info to show the progress bar in backannotating GSBs
|
2019-07-13 19:53:44 -06:00 |
tangxifan
|
aa4cd850ae
|
try to optimize the runtime of routing uniqueness detection
|
2019-07-13 18:10:34 -06:00 |
tangxifan
|
78578f66c5
|
bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
|
2019-07-13 14:48:32 -06:00 |
Baudouin Chauviere
|
f140e08093
|
Pre-Merge modifications
|
2019-07-12 10:48:43 -06:00 |
Baudouin Chauviere
|
a0f1f8d163
|
Fix when explicit verilog is NOT used
|
2019-07-12 10:39:31 -06:00 |
tangxifan
|
f0ecc51b51
|
bug fixing to resolve the conflicts between explicit port map and standard cell map
|
2019-07-12 10:38:20 -06:00 |
Baudouin Chauviere
|
40d3460bac
|
Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
|
2019-07-11 22:13:30 -06:00 |
Baudouin Chauviere
|
e461cd0b99
|
Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
|
2019-07-11 22:09:49 -06:00 |
Baudouin Chauviere
|
1431ee2f82
|
Fix Explicit verilog
|
2019-07-11 22:09:34 -06:00 |
tangxifan
|
cffdebd912
|
bug fixed for the tileable RR graph generator for heterogeneous blocks
|
2019-07-11 21:02:09 -06:00 |
Baudouin Chauviere
|
c9b84f61c9
|
Hot fix
|
2019-07-11 17:39:02 -06:00 |
Baudouin Chauviere
|
d0cd5a2bc1
|
Hot fix
|
2019-07-11 17:27:31 -06:00 |
tangxifan
|
9c203ca4d2
|
bug fixing in SDC generator
|
2019-07-11 17:10:08 -06:00 |
Baudouin Chauviere
|
f4be375637
|
Latest version explicit
|
2019-07-11 14:33:56 -06:00 |
tangxifan
|
31749fe62b
|
fix bugs in fpga_flow.pl
|
2019-07-10 21:12:00 -06:00 |
tangxifan
|
a90316e9f4
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-10 15:13:46 -06:00 |
tangxifan
|
acee0161c7
|
Merge branch 'tileable_routing' into dev
|
2019-07-10 15:13:24 -06:00 |
Baudouin Chauviere
|
6441f2ebe7
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-10 14:16:55 -06:00 |
Baudouin Chauviere
|
0a978db866
|
Fix regression test
|
2019-07-10 14:16:34 -06:00 |
tangxifan
|
b7f9831bd2
|
add statistics for unique GSBs
|
2019-07-10 13:08:03 -06:00 |
tangxifan
|
c6a4d29ed8
|
Merge branch 'tileable_routing' into dev
|
2019-07-10 12:05:43 -06:00 |
tangxifan
|
57ae5dbbec
|
bug fixing for rectangle FPGA sizes
|
2019-07-09 20:47:52 -06:00 |
tangxifan
|
edfe3144c3
|
update profiling, found where runtime is lost
|
2019-07-09 20:28:01 -06:00 |
tangxifan
|
737cc2874f
|
Merge branch 'tileable_routing' into dev
|
2019-07-09 17:42:44 -06:00 |
tangxifan
|
65f696c1d7
|
fix critical bugs in rectangle floorplan
|
2019-07-09 17:41:20 -06:00 |
Baudouin Chauviere
|
4ca0967453
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-09 14:35:51 -06:00 |
Baudouin Chauviere
|
792ba23f4f
|
Correction pre-merge
|
2019-07-09 14:34:34 -06:00 |
Baudouin Chauviere
|
589f58b55e
|
Regression test succeeded
|
2019-07-09 09:18:06 -06:00 |
Baudouin Chauviere
|
25f5bc7792
|
Latest version, not stable yet but close
|
2019-07-09 08:34:01 -06:00 |
tangxifan
|
5d5e09fcdb
|
minor fix in trying to accelerate the unique routing functions
|
2019-07-08 17:12:36 -06:00 |
Baudouin Chauviere
|
df0a3d23a3
|
Correction top module
|
2019-07-08 10:23:14 -06:00 |
Baudouin Chauviere
|
ae05c553d5
|
Top module done
|
2019-07-08 09:48:33 -06:00 |
tangxifan
|
76fefdb876
|
bug fixing in Fc_in and be serious in the performance of rr_graph
|
2019-07-05 16:23:15 -06:00 |
tangxifan
|
c62762ce59
|
bug fixing in assign ipins to tracks using Fc_in
|
2019-07-05 13:42:22 -06:00 |
tangxifan
|
64d8e9663a
|
minor fix to satisfy Fc_in and Fc_out
|
2019-07-05 13:13:35 -06:00 |
tangxifan
|
3077efa74f
|
add option to compact tileable routing arch
|
2019-07-04 17:13:34 -06:00 |
tangxifan
|
d64aeef5c4
|
add profiling to routing compact process
|
2019-07-03 16:57:34 -06:00 |
tangxifan
|
1a1da30ae9
|
fixed a critical bug in using tileable route chan W
|
2019-07-03 16:46:43 -06:00 |
tangxifan
|
b79d276ea9
|
add profiling to fpga_x2p_setup
|
2019-07-03 14:44:54 -06:00 |
tangxifan
|
4f3cb0bdf3
|
added tileable routing chanW adaption to fixed W router
|
2019-07-03 14:29:50 -06:00 |
tangxifan
|
0c3e8bb70a
|
add a new option to the router to enable conversion of route_chan_width to be tileable
|
2019-07-03 12:11:48 -06:00 |
tangxifan
|
02398818a9
|
update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area
|
2019-07-03 10:33:02 -06:00 |
tangxifan
|
4392c6bc3a
|
bug fixing in fpga_flow scripts and add more print-out message for VPR
|
2019-07-02 15:34:59 -06:00 |
Baudouin Chauviere
|
b08513d902
|
Big chunk added on the routing part of the explicit mapping
|
2019-07-02 14:12:42 -06:00 |
Baudouin Chauviere
|
8f5ad2eb67
|
Snapshot of progress
|
2019-07-02 10:10:48 -06:00 |
tangxifan
|
95674c4687
|
added Switch Block SubType and SubFs for tileable rr_graph generation
|
2019-07-02 10:00:02 -06:00 |
tangxifan
|
44301bfd77
|
updated SPICE generator to avoid issues on clb2clb_direct
|
2019-07-02 09:01:52 -06:00 |
tangxifan
|
5b25bbb120
|
bug fixed for direct connection in CBs and direct connection in top netlist
|
2019-07-01 17:25:00 -06:00 |
Baudouin Chauviere
|
f189ef1d8f
|
Done with the submodules
|
2019-07-01 14:24:09 -06:00 |
Baudouin Chauviere
|
370ce23646
|
Mux explicit verilog done
|
2019-07-01 13:58:24 -06:00 |
Baudouin Chauviere
|
863e8677c0
|
Further add new functions to tree
|
2019-07-01 12:12:36 -06:00 |
Baudouin Chauviere
|
0e04b88c8f
|
Include new files in the parameter spreading
|
2019-07-01 11:27:48 -06:00 |
tangxifan
|
1332ba62e8
|
update tileable rr_graph generator to improve routability and also enable assoicated testing
|
2019-06-27 17:52:25 -06:00 |
tangxifan
|
15c536e9b4
|
minor fixing in printing the rr_node stats
|
2019-06-27 16:34:21 -06:00 |
Baudouin Chauviere
|
04eb6d3488
|
Correction pre-merge
|
2019-06-27 14:33:06 -06:00 |
Baudouin Chauviere
|
7c742f1cbb
|
Stable, is_explicit propagated through the code. Not implemented though except for muxes
|
2019-06-27 10:29:57 -06:00 |
tangxifan
|
8edd85c9fc
|
keep fixing bugs in verilog SDC generator for tileable CBs
|
2019-06-26 22:58:52 -06:00 |
tangxifan
|
711e369fe7
|
fixing bugs in the SDC generator and report_timing
|
2019-06-26 18:09:09 -06:00 |
tangxifan
|
0fe54d87d5
|
fixed a bug in SDC generator for constraining SBs in tileable arch
|
2019-06-26 17:06:14 -06:00 |
Baudouin Chauviere
|
0ce9846e47
|
Stable, unfinished
|
2019-06-26 16:54:41 -06:00 |
tangxifan
|
7d85eb544d
|
start fixing bugs for SDC generator when using tileable arch
|
2019-06-26 16:48:17 -06:00 |
tangxifan
|
f5920c7422
|
fix bugs in ptc_num using for SB
|
2019-06-26 16:21:02 -06:00 |
tangxifan
|
3d8200e217
|
critical bug fixed in bitstream generator for compact routing hierarchy
|
2019-06-26 15:51:11 -06:00 |
tangxifan
|
d2ed82d14d
|
Merge branch 'tileable_routing' into multimode_clb
|
2019-06-26 15:00:39 -06:00 |
tangxifan
|
57616361c2
|
fixed critical bugs in cb configuration port indices
|
2019-06-26 14:58:52 -06:00 |
Baudouin Chauviere
|
d2bd2be76b
|
Warnings correction in the make sequence
|
2019-06-26 14:33:12 -06:00 |
Baudouin Chauviere
|
87ddca9f57
|
commiting current work. Stable but function not implemented yet
|
2019-06-26 14:22:02 -06:00 |
tangxifan
|
42f85004b6
|
fix bugs in finding the ending SB of a rr_node
|
2019-06-26 14:13:41 -06:00 |
tangxifan
|
9b6a4b39bb
|
Merge branch 'tileable_routing' into multimode_clb
|
2019-06-26 11:36:08 -06:00 |
tangxifan
|
c879e7f6c5
|
fixed a critical bug when instanciating Connection blocks
|
2019-06-26 11:33:02 -06:00 |
Baudouin Chauviere
|
b7c2954b91
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-26 10:51:55 -06:00 |
Baudouin Chauviere
|
8f21a3b177
|
Memory leakage correction
|
2019-06-26 10:50:38 -06:00 |
tangxifan
|
d50fb7ee19
|
fixed the bug in determine passing wires for rr_gsb
|
2019-06-26 10:50:23 -06:00 |
AurelienUoU
|
ec504049ef
|
Update Testbenches to increase accuracy + commented compact routing option until debug
|
2019-06-26 10:01:12 -06:00 |
tangxifan
|
a3670bb752
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-26 09:45:04 -06:00 |
Baudouin Chauviere
|
56557b94e7
|
Bug Fix
|
2019-06-26 08:53:46 -06:00 |
tangxifan
|
3c0ef2067d
|
fixed critical bugs in pass_tracks identification and update regression test for tileable arch
|
2019-06-25 21:59:38 -06:00 |
Baudouin Chauviere
|
bb250ddef9
|
Bug fix in cpp
|
2019-06-25 16:47:10 -06:00 |
tangxifan
|
4d3b5f12b4
|
fixed bugs for UNIVERSAL and WILTON switch blocks
|
2019-06-25 14:15:29 -06:00 |
Baudouin Chauviere
|
332ce17f03
|
Division between horizontal and vertical analysis
|
2019-06-25 13:44:41 -06:00 |
tangxifan
|
a88263a4c2
|
update rr_block writer to include IPINs in XML files
|
2019-06-25 11:17:22 -06:00 |
tangxifan
|
785b560bd5
|
sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now
|
2019-06-24 22:46:56 -06:00 |
tangxifan
|
fd301eeb66
|
many bug fixing and now start improving the routability of tileable rr_graph
|
2019-06-24 17:33:29 -06:00 |
tangxifan
|
0d62661c71
|
bug fixing and spot critical bugs in directlist parser
|
2019-06-23 20:52:38 -06:00 |
tangxifan
|
cdd4af9c58
|
vpr likes the tileable rr_graph while fpga_x2p does not
|
2019-06-23 18:11:13 -06:00 |
tangxifan
|
59df305668
|
bug fixing and reorganize rr_graph builder source files
|
2019-06-23 16:40:13 -06:00 |
tangxifan
|
2837f44df2
|
bug fixing for tileable rr_graph generator.
|
2019-06-22 20:41:06 -06:00 |
tangxifan
|
7c38b32eb1
|
keep bug fixing for tileable rr_graph generator
|
2019-06-21 22:51:11 -06:00 |
tangxifan
|
1b91c32121
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-21 17:59:55 -06:00 |
tangxifan
|
41954056ce
|
many bug fixing for tileable rr_graph generator. Still debugging
|
2019-06-21 17:58:46 -06:00 |
AurelienUoU
|
0a42f6a796
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-21 15:47:14 -06:00 |
AurelienUoU
|
c0d7099cd6
|
Allow CB on top of blocks with height > 1
|
2019-06-21 15:46:05 -06:00 |
tangxifan
|
d48fd959a9
|
keep bug fixing for tileable rr_graph generator
|
2019-06-20 22:30:26 -06:00 |
tangxifan
|
548242b368
|
plug-in tileable rr generator which can be enable by a XML property
|
2019-06-20 21:06:26 -06:00 |
tangxifan
|
cf82d87e11
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-20 18:18:20 -06:00 |
tangxifan
|
baab9c4a21
|
basically finished the coding of tileable rr_graph generator. testing to go
|
2019-06-20 18:17:07 -06:00 |
Baudouin Chauviere
|
be25b6dd66
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-06-20 14:11:03 -06:00 |
Baudouin Chauviere
|
3bd6c40a10
|
Report timing modified to have only one liners
|
2019-06-20 14:10:39 -06:00 |
AurelienUoU
|
a7502bb43b
|
Avoid configuration bits for module wihch don't require them
|
2019-06-20 09:40:41 -06:00 |
tangxifan
|
e7f2bd3b7c
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-19 21:31:54 -06:00 |
tangxifan
|
2f15d2d13c
|
keep developing tileable rr_graph, track2ipin and opin2track to go
|
2019-06-19 21:30:16 -06:00 |
AurelienUoU
|
ff00e4c79c
|
Free only if it's possible to free
|
2019-06-19 16:15:30 -06:00 |
tangxifan
|
ba15358564
|
developing ipin2track mapping for tiles
|
2019-06-18 18:06:21 -06:00 |
tangxifan
|
9ca1b42f4c
|
developing switch block pattern for tileable routing architecture
|
2019-06-18 16:52:42 -06:00 |
tangxifan
|
352c97302b
|
start building object GSB graph
|
2019-06-17 22:10:30 -06:00 |
tangxifan
|
f4191315da
|
use rr_gsb to build edges of rr_graph
|
2019-06-17 18:01:45 -06:00 |
tangxifan
|
51ff150a77
|
bug fixing in tileable rr_graph generator
|
2019-06-17 10:16:08 -06:00 |
tangxifan
|
0d14fef53e
|
bug fixing in setting CHANX and CHANY nodes in tileable rr_graph generator
|
2019-06-16 23:02:18 -06:00 |
tangxifan
|
04ffb99ca6
|
Merge branch 'multimode_clb' into tileable_routing
|
2019-06-16 16:01:30 -06:00 |
Baudouin Chauviere
|
57a4ad1f99
|
Break memories even in the clb sdc
|
2019-06-16 14:27:29 -06:00 |
tangxifan
|
1af3b5ef55
|
set chan_rr_nodes in tileable rr_graph builder
|
2019-06-16 14:23:19 -06:00 |
tangxifan
|
8c9cc003ea
|
developing routing track rr_node set up in tileable routing architecture
|
2019-06-15 18:11:08 -06:00 |
tangxifan
|
c8bf456097
|
bug fixing for memory leaking in allocating pb_rr_graph and power estimation
|
2019-06-15 12:23:36 -06:00 |
tangxifan
|
d3296d0975
|
developing tileable rr_graph builder
|
2019-06-14 22:35:42 -06:00 |
tangxifan
|
a33627606e
|
developing tileable routing track arrangement
|
2019-06-14 17:35:40 -06:00 |
tangxifan
|
4d2a3680be
|
support bus explicit port mapping to standard cells (for BRAMs)
|
2019-06-14 11:09:15 -06:00 |
tangxifan
|
0902d1e75a
|
c++ string is not working, use char which is stable
|
2019-06-13 18:38:46 -06:00 |
tangxifan
|
af1628abfe
|
use bus port for primitives in Verilog generator
|
2019-06-13 16:26:58 -06:00 |
tangxifan
|
dddbbac85c
|
merge from multimode_clb bug fixing
|
2019-06-13 15:59:34 -06:00 |
tangxifan
|
43128ad3f0
|
fix a bug in formal verification port for memory bank configuration circuits
|
2019-06-13 15:33:13 -06:00 |
tangxifan
|
44d21ebb90
|
fixed a bug in Verilog generator supporting SRAM5T
|
2019-06-13 14:42:39 -06:00 |
tangxifan
|
5ae4dec0af
|
fix bugs in CMakeList on enable/disable VPR Graphics
|
2019-06-12 22:48:00 -06:00 |
tangxifan
|
1d00e3665b
|
start developing tileable_rr_graph_builder
|
2019-06-11 16:50:40 -06:00 |
tangxifan
|
65b5454f3a
|
start developing tileable_rr_graph_builder
|
2019-06-11 16:49:10 -06:00 |
tangxifan
|
7245917b9c
|
fix a bug for iopad SPICE generation
|
2019-06-11 11:43:56 -06:00 |
tangxifan
|
1776ae3ec8
|
add explicit port mapping for inverters of memory decoders
|
2019-06-10 17:36:14 -06:00 |
tangxifan
|
8e3ad675e0
|
use sstream for rr_block verilog writer
|
2019-06-10 16:23:35 -06:00 |
tangxifan
|
009e5244d3
|
minor fix on the port direction of configuration peripherals for memory decoders
|
2019-06-10 15:39:35 -06:00 |
tangxifan
|
f43955037c
|
remove input port requirements for SRAM circuit module
|
2019-06-10 15:29:44 -06:00 |
tangxifan
|
e4f70771a2
|
updated SDC generator to embrace the RRGSB data structure
|
2019-06-10 14:47:27 -06:00 |
tangxifan
|
8a8f4153ce
|
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
|
2019-06-10 12:50:10 -06:00 |
tangxifan
|
e31407f693
|
start cleaning up SDC generator with new RRGSB data structure
|
2019-06-10 10:57:26 -06:00 |
tangxifan
|
17bc7fc296
|
update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
|
2019-06-08 20:11:22 -06:00 |
Xifan Tang
|
61e359efc5
|
Enable an option to disable/enable graphics in VPR compilation
|
2019-06-08 15:08:17 -06:00 |
tangxifan
|
8c5ec4572d
|
revert string to sprintf
|
2019-06-07 20:20:41 -06:00 |
tangxifan
|
0f1ed19ad0
|
Revert to the use of sprintf instead std::string. Have no idea why string is not working
|
2019-06-07 18:54:57 -06:00 |
tangxifan
|
44ce0e8834
|
update gsb unique module detection and fix formal verification port direction
|
2019-06-07 17:18:38 -06:00 |
tangxifan
|
24d53390d8
|
clean up DeviceRRGSB internal data and member functions
|
2019-06-07 14:45:56 -06:00 |
tangxifan
|
c9f810ceb6
|
update rr_gsb to build connection blocks
|
2019-06-07 11:01:55 -06:00 |
tangxifan
|
472aff5acb
|
add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
|
2019-06-06 23:45:21 -06:00 |
tangxifan
|
ce9fc5696c
|
rename rr_switch_block to rr_gsb, a generic block
|
2019-06-06 17:41:01 -06:00 |
tangxifan
|
8c1e7b799f
|
fixed critical bugs in Connection Block Unique Module detection
|
2019-06-06 16:31:50 -06:00 |
tangxifan
|
873e4d989f
|
fine-tuning Verilog format and node addition to rr_blocks
|
2019-06-06 12:48:41 -06:00 |
tangxifan
|
c2de0eefb1
|
fix redundant comma in SB Verilog module
|
2019-06-06 09:15:05 -06:00 |
tangxifan
|
b9e1b1afc4
|
fix a critical bug in num_reserved_sram_ports
|
2019-06-05 17:31:01 -06:00 |
tangxifan
|
aaf8d23971
|
fix critical bugs in routing submodules
|
2019-06-05 16:43:18 -06:00 |
tangxifan
|
01e075377d
|
fix typo in Verilog generation
|
2019-06-05 15:30:34 -06:00 |
tangxifan
|
21d0cb52bc
|
Merge remote-tracking branch 'origin' into tileable_sb
|
2019-06-05 13:31:49 -06:00 |
tangxifan
|
24ca3104b0
|
fix minor bugs in Switch Block submodules
|
2019-06-05 13:30:55 -06:00 |
tangxifan
|
0f87ae9886
|
support switch block submodule Verilog generation by segments
|
2019-06-05 12:56:05 -06:00 |
AurelienUoU
|
84fabbd43b
|
Fix sdc analysis bug related to virtual nodes + add the option in regression test
|
2019-06-05 12:10:28 -06:00 |
Baudouin Chauviere
|
d24488092d
|
Fix bug
|
2019-06-05 11:40:04 -06:00 |
tangxifan
|
c2d8fa00ba
|
add rr_block unique_side_module verilog generation
|
2019-06-04 17:47:40 -06:00 |
tangxifan
|
98b82c17be
|
bug fixing for clear RRSwitchBlock
|
2019-06-04 14:02:49 -06:00 |
tangxifan
|
2c6780ab92
|
add side mirror detection for RRSwitchBlock
|
2019-06-04 13:01:22 -06:00 |
Baudouin Chauviere
|
1932d00309
|
Correction of the SDC to remove global clocks
|
2019-05-30 15:04:21 -06:00 |
tangxifan
|
5b15a746d3
|
add num_driver_nodes to Switch Block XML writter
|
2019-05-28 20:52:33 -06:00 |
tangxifan
|
5ed076dfb4
|
fixed a critical bug in rotating
|
2019-05-28 17:55:09 -06:00 |
tangxifan
|
9cc5518d5a
|
keep adding segment information for SB XML outputter
|
2019-05-28 15:59:55 -06:00 |
tangxifan
|
e7e18eb4c1
|
Add more information in SB XML outputter
|
2019-05-28 15:56:41 -06:00 |
tangxifan
|
ca363da30c
|
add options to specify output directory of SB XML
|
2019-05-28 15:19:10 -06:00 |
tangxifan
|
6b51b42ee7
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-28 14:53:44 -06:00 |
tangxifan
|
af91fca1e0
|
add rr_blocks XML writer to help debugging Switch Block Rotation
|
2019-05-28 14:52:44 -06:00 |
Baudouin Chauviere
|
3da216f297
|
correction Null issue for the flat model
|
2019-05-28 14:15:24 -06:00 |
tangxifan
|
6f30d3ad05
|
support rotation on segment groups inside RRChan and improve rotatable mirror searching
|
2019-05-28 11:25:16 -06:00 |
tangxifan
|
0f5666ea11
|
fixed the bug in mirror node direction
|
2019-05-27 21:58:21 -06:00 |
tangxifan
|
eece161d58
|
keep debugging on Switch Block rotation
|
2019-05-27 21:10:30 -06:00 |
tangxifan
|
5720217cfd
|
Add copy constructor for RRChan, RRSwitchBlock etc.
|
2019-05-27 15:44:34 -06:00 |
tangxifan
|
1bea9870fc
|
developed new rotating methods for RRSwitchBlocks, debugging ongoing
|
2019-05-26 23:35:30 -06:00 |
tangxifan
|
4b852afeac
|
skip rotating mirror detection which is too time-consuming
|
2019-05-25 23:41:46 -06:00 |
tangxifan
|
22e71f5847
|
Add rotate one side of switch block functionality
|
2019-05-25 22:48:07 -06:00 |
tangxifan
|
858a323228
|
Add more support for rotating Switch Blocks
|
2019-05-25 21:26:35 -06:00 |
tangxifan
|
2eab0b1c1c
|
update unique_mirror search algorithm for Switch Blocks
|
2019-05-25 19:54:15 -06:00 |
tangxifan
|
d3eae80e64
|
implemented an native way in finding rotable Switch blocks
|
2019-05-25 19:37:18 -06:00 |
tangxifan
|
ae0248fbc6
|
debugging SwitchBlock rotating
|
2019-05-24 23:10:30 -06:00 |
tangxifan
|
9adc2945c8
|
add rotate functionality for RRSwitchBlock
|
2019-05-24 21:40:16 -06:00 |
tangxifan
|
02b48d036d
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
tangxifan
|
2c46da6888
|
clean-up warnings Verilog routing generator
|
2019-05-24 16:29:17 -06:00 |
tangxifan
|
27b996337a
|
fixed a critical bug in Compact Verilog generation for SB/CBs
|
2019-05-24 16:14:46 -06:00 |
tangxifan
|
1ade1f1d3f
|
update SDC generator disabled_unused_mux by using RRSwitchBlock
|
2019-05-24 15:42:00 -06:00 |
tangxifan
|
f27b88db8d
|
Use RRChan in SDC generator to replace old data structures
|
2019-05-24 15:34:56 -06:00 |
tangxifan
|
27c234711e
|
clean up warnings in SDC pb_type generator
|
2019-05-24 15:23:38 -06:00 |
tangxifan
|
924136e7a2
|
Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
|
2019-05-24 15:10:08 -06:00 |
tangxifan
|
994b90ae53
|
updated report_timing for using RRSwitchBlock
|
2019-05-24 14:25:51 -06:00 |
tangxifan
|
eef1312325
|
updated bitstream to use new RRSwitchBlock as well as the report timing engine
|
2019-05-24 12:54:10 -06:00 |
tangxifan
|
8f4f590ff9
|
update Verilog compact_netlist outputter with RRSwitchBlock classes
|
2019-05-23 21:52:12 -06:00 |
tangxifan
|
ea8c36ce6e
|
upgrade Verilog SB generator using the RRSwitchBlock
|
2019-05-23 17:37:39 -06:00 |
tangxifan
|
4aab93b729
|
update class rr_switch_block and be ready for updating the downstream verilog generator
|
2019-05-22 22:04:31 -06:00 |
tangxifan
|
efbc454cdd
|
Add Class for RRSwtichBlock and plug-in to replace the old t_sb
|
2019-05-22 12:34:06 -06:00 |
tangxifan
|
ec3b4c86c4
|
update file organization and be ready for SB/CB class
|
2019-05-21 12:15:38 -06:00 |
tangxifan
|
8186d6dd11
|
reorganize files and clean some warnings
|
2019-05-21 10:17:54 -06:00 |
tangxifan
|
b185a17359
|
add routing_channel unique module generation
|
2019-05-20 22:33:17 -06:00 |
giacomin
|
ceee28226e
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-20 16:47:07 -06:00 |
giacomin
|
8b520349e7
|
fixed a bug for rram based fpga when using explicit verilog port mapping
|
2019-05-20 16:44:47 -06:00 |
AurelienUoU
|
99beeb48cc
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-13 16:42:27 -06:00 |
AurelienUoU
|
a3656dde45
|
Add missing Verilog source, Archictecture folder and Testbenches correction
|
2019-05-13 16:41:35 -06:00 |
Baudouin Chauviere
|
b48a27acf0
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-13 14:45:57 -06:00 |
Baudouin Chauviere
|
2019840d7c
|
cleaned unused variables
|
2019-05-13 14:45:02 -06:00 |
tangxifan
|
3313eac23b
|
add rr_chan obj
|
2019-05-10 22:50:08 -06:00 |
AurelienUoU
|
9c05a4fb0a
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-10 14:09:23 -06:00 |
AurelienUoU
|
ff9b84d800
|
Bug fix in Icarus requirement
|
2019-05-10 14:07:32 -06:00 |
tangxifan
|
be4643b8a6
|
updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated
|
2019-05-10 10:21:06 -06:00 |
tangxifan
|
5c646f5de7
|
fix bugs in routing identification
|
2019-05-09 21:40:06 -06:00 |
tangxifan
|
a9df922412
|
finish the identification on mirror switch and connection blocks
Verilog generator to be updated
|
2019-05-09 21:31:39 -06:00 |
tangxifan
|
a3c3f2b892
|
developing compact routing hierarchy
|
2019-05-08 20:49:21 -06:00 |
tangxifan
|
4c6639218e
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-08 14:30:33 -06:00 |
tangxifan
|
e305e60ee4
|
minor fix on the shell interface of VPR
|
2019-05-08 14:29:58 -06:00 |
Baudouin Chauviere
|
4f386de2ef
|
gen_xxx functions create mem-leaks because the mem is dynamically allocated inside and not freed. TBD later everywhere
|
2019-05-06 17:25:29 -06:00 |
Baudouin Chauviere
|
3b62f8e024
|
Conversion from s to ns for the loop breaking delays
|
2019-05-06 16:12:30 -06:00 |
Baudouin Chauviere
|
a5a1a376ab
|
Modified code for cleaner delay naming convention
|
2019-05-06 12:52:49 -06:00 |
tangxifan
|
4e3487b691
|
Add latest abc and update ace dependence
|
2019-05-03 18:56:03 -06:00 |
Baudouin Chauviere
|
7860042276
|
added before after loop breaker constraining
|
2019-05-03 14:00:06 -06:00 |
Baudouin Chauviere
|
4e330ee463
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-05-03 10:43:22 -06:00 |
Baudouin Chauviere
|
921b694400
|
Bug fix sdc breaking loop of edges outside current interconnect
|
2019-05-03 10:42:35 -06:00 |
AurelienUoU
|
42f20eda60
|
Add the user matching for internal register in formal verification script generation
|
2019-05-03 10:24:02 -06:00 |
tangxifan
|
974af5a2ae
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
|
2019-04-30 14:30:38 -06:00 |
tangxifan
|
42daadee2f
|
critical bug fixing
|
2019-04-30 14:30:17 -06:00 |
Baudouin Chauviere
|
1ab4688339
|
Create no segment constraint in loop_breaker if none is given by user
|
2019-04-30 12:30:07 -06:00 |
tangxifan
|
c46c0fc97d
|
bug fixing for SDC generator
|
2019-04-26 14:07:44 -06:00 |
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
tangxifan
|
b06df18a89
|
Update rr_graph_area.c
|
2019-03-11 21:46:42 +08:00 |
AurelienUoU
|
213f94ddee
|
Correct preconfiguration
|
2019-01-31 16:43:47 -07:00 |
tangxifan
|
5e36aa82c5
|
fixa bug in determining mux structure
|
2019-01-22 13:54:50 -07:00 |
tangxifan
|
b8187bbca5
|
fix a bug for supporting default circuit_model of LUTs and FFs
|
2019-01-10 15:10:05 -07:00 |
AurelienUoU
|
b80e435548
|
Correct manual testbench generation bug
|
2019-01-07 18:03:56 -07:00 |
AurelienUoU
|
21dc8a006f
|
Change simulator script generation (waves)
|
2018-12-14 14:40:04 -07:00 |
tangxifan
|
ee6b1d6cd6
|
adapt arch xml and act for demo
|
2018-12-13 22:46:40 -07:00 |
AurelienUoU
|
cc5a01d476
|
Fix waveform generation + add benchmark and update go.sh
|
2018-12-11 22:21:39 -07:00 |
AurelienUoU
|
f5ea3ff233
|
Add an autochecked configuration free testbench
|
2018-12-11 14:44:13 -07:00 |
tangxifan
|
72fbd8d6a8
|
update blif reader to identify clock signals
|
2018-12-10 13:28:44 -07:00 |
AurelienUoU
|
a69c2e1882
|
Add security in checking to avoid simulation glitch error
|
2018-12-10 09:46:16 -07:00 |
AurelienUoU
|
7020d9b4b6
|
Edit waveform generator + fix clock mapping in autochecked testbench
|
2018-12-09 15:48:59 -07:00 |
AurelienUoU
|
5e94b7093d
|
Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
|
2018-12-08 22:57:54 -07:00 |
Aur??Lien ALACCHI
|
10866d1852
|
Correct verilog syntax error in autocheck testbench
|
2018-12-08 17:40:23 -07:00 |
Aur??Lien ALACCHI
|
d716b67e23
|
Correct syntax error in autocheck testbench
|
2018-12-08 17:29:56 -07:00 |
Aur??Lien ALACCHI
|
0580d8243f
|
Add Autochek testbench option
|
2018-12-08 17:19:12 -07:00 |
Aur??Lien ALACCHI
|
4cc875a5a5
|
fix a bug in wired LUT
|
2018-12-06 18:00:17 -07:00 |
tangxifan
|
b3c1018e28
|
fixed a bug in wired LUT
|
2018-12-06 16:50:30 -07:00 |
Aur??Lien ALACCHI
|
eebdf7cb10
|
Add possibility to choose default value for initialization
|
2018-12-06 15:34:14 -07:00 |
Baudouin Chauviere
|
b6bb419e1d
|
add a ModelSim option
|
2018-12-06 14:13:37 -07:00 |
Aur??Lien ALACCHI
|
8281b7346b
|
Edit auto-generated modelsim script
|
2018-12-05 16:15:29 -07:00 |
Aur??Lien ALACCHI
|
44b7f7f3d4
|
Correct sub_modules.v generation to include decoders.v when necessary
|
2018-12-05 13:52:25 -07:00 |
Aur??Lien ALACCHI
|
dc4accedd9
|
Add forgottent files + add parameter transmission from verilog_api.c
|
2018-12-05 11:33:14 -07:00 |
Aur??Lien ALACCHI
|
9a8c7b391a
|
Add process for modelsim script autogeneration
|
2018-12-05 09:20:47 -07:00 |
Aur??Lien ALACCHI
|
75d64db0f9
|
Add verilog header sub_module.v file generation
|
2018-12-04 18:42:47 -07:00 |
Aur??Lien ALACCHI
|
8ac566ecc0
|
Add timing and initialization for simulation
|
2018-12-04 17:32:09 -07:00 |
tangxifan
|
70751551b5
|
fix a bug in wired LUT support
|
2018-11-30 21:33:31 -07:00 |
tangxifan
|
e223868df8
|
fix bugs for wired LUTs
|
2018-11-27 12:46:30 -07:00 |
Aur??Lien ALACCHI
|
de2bc18bbb
|
bugs fixed for shift register benchmark
|
2018-11-26 16:58:45 -07:00 |
tangxifan
|
861c449606
|
support wired LUT in FPGA-SPICE and FPGA-Verilog
|
2018-11-15 15:57:49 -07:00 |
Baudouin Chauviere
|
f7d7a056da
|
Modification of the fpga_spice_utils
|
2018-11-15 14:11:55 -07:00 |
Baudouin Chauviere
|
c81d00bb51
|
Correction of the double free bug
|
2018-11-15 13:55:16 -07:00 |
tangxifan
|
c67ba5f58a
|
clean up codes
|
2018-09-27 14:26:08 -06:00 |
tangxifan
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681cca99a4
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fix a bug in tapbuf
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2018-09-21 19:00:22 -06:00 |
tangxifan
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d683134b12
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rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |