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bug fixing

This commit is contained in:
tangxifan 2019-07-17 08:25:52 -06:00
parent 6e1d49d74e
commit dcc96bf7f5
3 changed files with 17 additions and 3 deletions
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10
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c
View File

@ -440,7 +440,15 @@ void config_spice_model_input_output_buffers_pass_gate(int num_spice_models,
exit(1);
}
/* Copy the information from found spice model to current spice model*/
memcpy(spice_model[i].pass_gate_logic, pgl_spice_model->design_tech_info.pass_gate_info, sizeof(t_spice_model_pass_gate_logic));
/* copy gate info if this is a standard cell */
if (SPICE_MODEL_GATE == pgl_spice_model->type) {
assert ( SPICE_MODEL_GATE_MUX2 == pgl_spice_model->design_tech_info.gate_info->type);
spice_model[i].design_tech_info.gate_info = (t_spice_model_gate*)my_calloc(1, sizeof(t_spice_model_gate));
memcpy(spice_model[i].design_tech_info.gate_info, pgl_spice_model->design_tech_info.gate_info, sizeof(t_spice_model_gate));
} else {
assert (SPICE_MODEL_PASSGATE == pgl_spice_model->type);
memcpy(spice_model[i].pass_gate_logic, pgl_spice_model->design_tech_info.pass_gate_info, sizeof(t_spice_model_pass_gate_logic));
}
/* Recover the spice_model_name */
spice_model[i].pass_gate_logic->spice_model_name = my_strdup(pgl_spice_model->name);
spice_model[i].pass_gate_logic->spice_model = pgl_spice_model;

7
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -1250,6 +1250,9 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
int num_output_port = 0;
t_spice_model_port** input_port = NULL;
t_spice_model_port** output_port = NULL;
input_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
output_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
/* Quick check on the number of ports */
assert(3 == num_input_port); /* A, B and SEL */
assert(1 == num_output_port); /* OUT */
@ -1268,7 +1271,9 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
fprintf(fp, "mux2_l%d_in[%d]", level, j); /* input0 */
}
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(", input_port[1]->lib_name);
fprintf(fp, "), .%s(", input_port[1]->lib_name);
} else {
fprintf(fp, ", ");
}
/* For intermediate buffers */
if (TRUE == inter_buf_loc[level]) {

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -2924,7 +2924,8 @@ char* generate_verilog_mux_subckt_name(t_spice_model* spice_model,
/* If the tgate spice model of this MUX is a MUX2 standard cell,
* the mux_subckt name will be the name of the standard cell
*/
if ( SPICE_MODEL_GATE_MUX2 == spice_model->pass_gate_logic->spice_model->type) {
if ( SPICE_MODEL_GATE == spice_model->pass_gate_logic->spice_model->type) {
assert ( SPICE_MODEL_GATE_MUX2 == spice_model->design_tech_info.gate_info->type);
mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name);
} else {
mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5