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OpenFPGA
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memory sanitized

This commit is contained in:
tangxifan 2019-08-13 14:19:40 -06:00
parent ef4d15df4e
commit c7526cb43c
7 changed files with 15 additions and 10 deletions
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2
vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp
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@ -450,7 +450,7 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) {
num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_WIRE);
/* If we have any errors, exit */
vpr_printf(TIO_MESSAGE_ERROR,
vpr_printf(TIO_MESSAGE_INFO,
"Finished checking circuit library with %d errors!\n",
num_err);

11
vpr7_x2p/libarchfpga/SRC/circuit_library.cpp
View File

@ -48,6 +48,9 @@
/************************************************************************
* Constructors
***********************************************************************/
CircuitLibrary::CircuitLibrary() {
return;
}
/************************************************************************
* Public Accessors : aggregates
@ -1272,7 +1275,7 @@ void CircuitLibrary::set_wire_type(const CircuitModelId& circuit_model_id,
VTR_ASSERT(valid_circuit_model_id(circuit_model_id));
/* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */
VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id))
|| (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) );
|| (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) );
wire_types_[circuit_model_id] = wire_type;
return;
}
@ -1283,7 +1286,7 @@ void CircuitLibrary::set_wire_r(const CircuitModelId& circuit_model_id,
VTR_ASSERT(valid_circuit_model_id(circuit_model_id));
/* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */
VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id))
|| (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) );
|| (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) );
wire_rc_[circuit_model_id].set_x(r_val);
return;
}
@ -1294,7 +1297,7 @@ void CircuitLibrary::set_wire_c(const CircuitModelId& circuit_model_id,
VTR_ASSERT(valid_circuit_model_id(circuit_model_id));
/* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */
VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id))
|| (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) );
|| (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) );
wire_rc_[circuit_model_id].set_y(c_val);
return;
}
@ -1305,7 +1308,7 @@ void CircuitLibrary::set_wire_num_levels(const CircuitModelId& circuit_model_id,
VTR_ASSERT(valid_circuit_model_id(circuit_model_id));
/* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */
VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id))
|| (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) );
|| (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) );
wire_num_levels_[circuit_model_id] = num_level;
return;
}

1
vpr7_x2p/libarchfpga/SRC/circuit_library.h
View File

@ -216,6 +216,7 @@ class CircuitLibrary {
INPUT = 0, OUTPUT, LUT_INPUT_BUFFER, LUT_INPUT_INVERTER, LUT_INTER_BUFFER, NUM_BUFFER_TYPE /* Last one is a counter */
};
public: /* Constructors */
CircuitLibrary();
public: /* Accessors: aggregates */
circuit_model_range circuit_models() const;
circuit_port_range ports(const CircuitModelId& circuit_model_id) const;

2
vpr7_x2p/libarchfpga/SRC/circuit_types.h
View File

@ -114,7 +114,7 @@ enum e_spice_model_gate_type {
enum e_wire_model_type {
WIRE_MODEL_PIE,
WIRE_MODEL_T,
NUM_WIRE_MODEL_TYPES,
NUM_WIRE_MODEL_TYPES
};
enum e_spice_model_port_type {

5
vpr7_x2p/libarchfpga/SRC/read_xml_spice.c
View File

@ -1028,7 +1028,6 @@ static void ProcessSpiceModel(ezxml_t Parent,
}
ezxml_set_attr(Node, "fracturable_lut", NULL);
spice_model->design_tech_info.gate_info = NULL;
if (SPICE_MODEL_GATE == spice_model->type) {
/* Malloc */
@ -1073,13 +1072,15 @@ static void ProcessSpiceModel(ezxml_t Parent,
/* LUT intermediate buffers */
Node = ezxml_child(Parent, "lut_intermediate_buffer");
spice_model->lut_intermediate_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer));
spice_model->lut_intermediate_buffer = NULL;
if (Node) {
spice_model->lut_intermediate_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer));
/* Malloc the lut_input_buffer */
ProcessSpiceModelBuffer(Node,spice_model->lut_intermediate_buffer);
FreeNode(Node);
} else if ((SPICE_MODEL_LUT == spice_model->type)
|| (SPICE_MODEL_MUX == spice_model->type)) {
spice_model->lut_intermediate_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer));
/* Assign default values */
spice_model->lut_intermediate_buffer->exist = 0;
spice_model->lut_intermediate_buffer->spice_model = NULL;

2
vpr7_x2p/vpr/SRC/base/SetupVPR.c
View File

@ -1186,7 +1186,7 @@ static void SetupSynVerilogOpts(t_options Options,
/* SynVerilog needs the input from spice modeling */
if (FALSE == arch->read_xml_spice) {
arch->read_xml_spice = syn_verilog_opts->dump_syn_verilog;
arch->spice = (t_spice*)my_malloc(sizeof(t_spice));
arch->spice = (t_spice*)my_calloc(1, sizeof(t_spice));
}
return;

2
vpr7_x2p/vpr/SRC/ctags_vpr_src.sh
View File

@ -1,2 +1,2 @@
rm tags
ctags -R shell_main.c main.c ./* ../../libarchfpga/SRC/*.[ch] ../../pcre/SRC/*.[ch]
ctags -R shell_main.c main.c ./* ../../libarchfpga/SRC/* ../../pcre/SRC/*.[ch]