From c7526cb43cd531e4d35207a57a8682625cc5a4a2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Aug 2019 14:19:40 -0600 Subject: [PATCH] memory sanitized --- vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp | 2 +- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 11 +++++++---- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 1 + vpr7_x2p/libarchfpga/SRC/circuit_types.h | 2 +- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 5 +++-- vpr7_x2p/vpr/SRC/base/SetupVPR.c | 2 +- vpr7_x2p/vpr/SRC/ctags_vpr_src.sh | 2 +- 7 files changed, 15 insertions(+), 10 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index 98952927f..0b0f8fa69 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -450,7 +450,7 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_WIRE); /* If we have any errors, exit */ - vpr_printf(TIO_MESSAGE_ERROR, + vpr_printf(TIO_MESSAGE_INFO, "Finished checking circuit library with %d errors!\n", num_err); diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 6bd5aab07..4da76e417 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -48,6 +48,9 @@ /************************************************************************ * Constructors ***********************************************************************/ +CircuitLibrary::CircuitLibrary() { + return; +} /************************************************************************ * Public Accessors : aggregates @@ -1272,7 +1275,7 @@ void CircuitLibrary::set_wire_type(const CircuitModelId& circuit_model_id, VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_types_[circuit_model_id] = wire_type; return; } @@ -1283,7 +1286,7 @@ void CircuitLibrary::set_wire_r(const CircuitModelId& circuit_model_id, VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_rc_[circuit_model_id].set_x(r_val); return; } @@ -1294,7 +1297,7 @@ void CircuitLibrary::set_wire_c(const CircuitModelId& circuit_model_id, VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_rc_[circuit_model_id].set_y(c_val); return; } @@ -1305,7 +1308,7 @@ void CircuitLibrary::set_wire_num_levels(const CircuitModelId& circuit_model_id, VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); + || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); wire_num_levels_[circuit_model_id] = num_level; return; } diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 0b3ed3c06..1717bb60f 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -216,6 +216,7 @@ class CircuitLibrary { INPUT = 0, OUTPUT, LUT_INPUT_BUFFER, LUT_INPUT_INVERTER, LUT_INTER_BUFFER, NUM_BUFFER_TYPE /* Last one is a counter */ }; public: /* Constructors */ + CircuitLibrary(); public: /* Accessors: aggregates */ circuit_model_range circuit_models() const; circuit_port_range ports(const CircuitModelId& circuit_model_id) const; diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_types.h b/vpr7_x2p/libarchfpga/SRC/circuit_types.h index 6d72b2242..a2b86f38f 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_types.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_types.h @@ -114,7 +114,7 @@ enum e_spice_model_gate_type { enum e_wire_model_type { WIRE_MODEL_PIE, WIRE_MODEL_T, - NUM_WIRE_MODEL_TYPES, + NUM_WIRE_MODEL_TYPES }; enum e_spice_model_port_type { diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index b2e66728c..17ebb718a 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -1028,7 +1028,6 @@ static void ProcessSpiceModel(ezxml_t Parent, } ezxml_set_attr(Node, "fracturable_lut", NULL); - spice_model->design_tech_info.gate_info = NULL; if (SPICE_MODEL_GATE == spice_model->type) { /* Malloc */ @@ -1073,13 +1072,15 @@ static void ProcessSpiceModel(ezxml_t Parent, /* LUT intermediate buffers */ Node = ezxml_child(Parent, "lut_intermediate_buffer"); - spice_model->lut_intermediate_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer)); + spice_model->lut_intermediate_buffer = NULL; if (Node) { + spice_model->lut_intermediate_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer)); /* Malloc the lut_input_buffer */ ProcessSpiceModelBuffer(Node,spice_model->lut_intermediate_buffer); FreeNode(Node); } else if ((SPICE_MODEL_LUT == spice_model->type) || (SPICE_MODEL_MUX == spice_model->type)) { + spice_model->lut_intermediate_buffer = (t_spice_model_buffer*)my_calloc(1, sizeof(t_spice_model_buffer)); /* Assign default values */ spice_model->lut_intermediate_buffer->exist = 0; spice_model->lut_intermediate_buffer->spice_model = NULL; diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 7a78d6d97..5b0e90004 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -1186,7 +1186,7 @@ static void SetupSynVerilogOpts(t_options Options, /* SynVerilog needs the input from spice modeling */ if (FALSE == arch->read_xml_spice) { arch->read_xml_spice = syn_verilog_opts->dump_syn_verilog; - arch->spice = (t_spice*)my_malloc(sizeof(t_spice)); + arch->spice = (t_spice*)my_calloc(1, sizeof(t_spice)); } return; diff --git a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh index 919a90230..95bff29de 100755 --- a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh +++ b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh @@ -1,2 +1,2 @@ rm tags -ctags -R shell_main.c main.c ./* ../../libarchfpga/SRC/*.[ch] ../../pcre/SRC/*.[ch] +ctags -R shell_main.c main.c ./* ../../libarchfpga/SRC/* ../../pcre/SRC/*.[ch]