bug fixing herited from explicit mapping

2019-07-17 09:26:05 -06:00 · 2019-07-17 09:26:05 -06:00 · 32e3a556b9
parent 8b8e18a8de
commit 32e3a556b9
1 changed files with 1 additions and 1 deletions
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
@ -3213,7 +3213,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
                                                         cur_num_sram, 
                                                         cur_num_sram + num_mux_conf_bits - 1);
  
-  fprintf(fp, "is_explicit_mappingf\n");
+  fprintf(fp, "`endif\n");


  /* Call the MUX SPICE model */