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OpenFPGA
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bug fixing and get ready for testing

This commit is contained in:
tangxifan 2019-08-03 16:29:21 -06:00
parent c08c136844
commit 890ff05628
4 changed files with 20 additions and 4 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_mux_utils.c
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@ -340,7 +340,7 @@ int* decode_multilevel_mux_sram_bits(int fan_in,
* For example: when path_id=3, using a 4-input encoder
* the sram_bits will be the 4-digit binary number of 3: 0011
*/
int* tmp_bits = my_itobin_int(path_id, num_bits_per_level);
int* tmp_bits = my_itobin_int(encoded_path_id, num_bits_per_level);
/* Copy tmp_bits to encoded bits */
for (int idx = 0; idx < num_bits_per_level; ++idx) {
encoded_ret[idx + ilvl* num_bits_per_level] = tmp_bits[idx];

1
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c
View File

@ -582,6 +582,7 @@ int* my_itobin_int(int in_int, int bin_len) {
int i, temp;
/* Make sure we do not have any overflow! */
if (! ( (-1 < in_int) && (in_int < pow(2., bin_len)) ) )
assert ( (-1 < in_int) && (in_int < pow(2., bin_len)) );
temp = in_int;

17
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -1485,6 +1485,11 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp,
sram_port[0]->prefix,
sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx,
sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx);
} else {
fprintf(fp, "%s, %s_data[%d:%d], %s_data_inv[%d:%d]);\n",
sram_port[0]->prefix,
sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx,
sram_port[0]->prefix, sram_idx + cur_num_input_basis - 1, sram_idx);
}
}
/* Print basis muxQto1 for each level*/
@ -1716,6 +1721,11 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp,
sram_port[0]->prefix,
sram_port[0]->prefix,
sram_port[0]->prefix);
} else {
fprintf(fp, "%s, %s_data, %s_data_inv);\n",
sram_port[0]->prefix,
sram_port[0]->prefix,
sram_port[0]->prefix);
}
}
}
@ -2838,12 +2848,14 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) {
}
/* Print the name of encoder */
fprintf(fp, "//-------- Local Decoder convert %d-bit addr to %d-bit data \n",
num_inputs, num_outputs);
fprintf(fp, "module %s(", generate_verilog_decoder_subckt_name(num_inputs, num_outputs));
fprintf(fp, "\n");
/* Inputs */
dump_verilog_generic_port(fp, VERILOG_PORT_INPUT,
"addr",
num_inputs - 1, 0);
0, num_inputs - 1);
fprintf(fp, ",\n");
/* Outputs */
dump_verilog_generic_port(fp, VERILOG_PORT_OUTPUT,
@ -2893,6 +2905,9 @@ void dump_verilog_mux_local_encoder_module(FILE* fp, int num_outputs) {
/* Finish */
fprintf(fp, "endmodule\n");
fprintf(fp, "//-------- END Local Decoder convert %d-bit addr to %d-bit data \n\n",
num_inputs, num_outputs);
return;
}

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -2920,9 +2920,9 @@ char* generate_verilog_decoder_subckt_name(int addr_len, int data_len) {
char* subckt_name = NULL;
subckt_name = (char*)my_malloc(sizeof(char)*(strlen("decoder")
+ strlen(my_itoa(addr_len)) + 1
+ strlen(my_itoa(addr_len)) + 2
+ strlen(my_itoa(data_len)) + 1));
sprintf(subckt_name, "%s%d_%d",
sprintf(subckt_name, "%s%dto%d",
"decoder", addr_len, data_len);
return subckt_name;